dt-bindings/clock/ingenic%2Cjz4780-cgu.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * This header provides clock numbers for the ingenic,jz4780-cgu DT binding.
0004  *
0005  * They are roughly ordered as:
0006  *   - external clocks
0007  *   - PLLs
0008  *   - muxes/dividers in the order they appear in the jz4780 programmers manual
0009  *   - gates in order of their bit in the CLKGR* registers
0010  */
0011
0012 #ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
0013 #define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
0014
0015 #define JZ4780_CLK_EXCLK        0
0016 #define JZ4780_CLK_RTCLK        1
0017 #define JZ4780_CLK_APLL         2
0018 #define JZ4780_CLK_MPLL         3
0019 #define JZ4780_CLK_EPLL         4
0020 #define JZ4780_CLK_VPLL         5
0021 #define JZ4780_CLK_OTGPHY       6
0022 #define JZ4780_CLK_SCLKA        7
0023 #define JZ4780_CLK_CPUMUX       8
0024 #define JZ4780_CLK_CPU          9
0025 #define JZ4780_CLK_L2CACHE      10
0026 #define JZ4780_CLK_AHB0         11
0027 #define JZ4780_CLK_AHB2PMUX     12
0028 #define JZ4780_CLK_AHB2         13
0029 #define JZ4780_CLK_PCLK         14
0030 #define JZ4780_CLK_DDR          15
0031 #define JZ4780_CLK_VPU          16
0032 #define JZ4780_CLK_I2SPLL       17
0033 #define JZ4780_CLK_I2S          18
0034 #define JZ4780_CLK_LCD0PIXCLK   19
0035 #define JZ4780_CLK_LCD1PIXCLK   20
0036 #define JZ4780_CLK_MSCMUX       21
0037 #define JZ4780_CLK_MSC0         22
0038 #define JZ4780_CLK_MSC1         23
0039 #define JZ4780_CLK_MSC2         24
0040 #define JZ4780_CLK_UHC          25
0041 #define JZ4780_CLK_SSIPLL       26
0042 #define JZ4780_CLK_SSI          27
0043 #define JZ4780_CLK_CIMMCLK      28
0044 #define JZ4780_CLK_PCMPLL       29
0045 #define JZ4780_CLK_PCM          30
0046 #define JZ4780_CLK_GPU          31
0047 #define JZ4780_CLK_HDMI         32
0048 #define JZ4780_CLK_BCH          33
0049 #define JZ4780_CLK_NEMC         34
0050 #define JZ4780_CLK_OTG0         35
0051 #define JZ4780_CLK_SSI0         36
0052 #define JZ4780_CLK_SMB0         37
0053 #define JZ4780_CLK_SMB1         38
0054 #define JZ4780_CLK_SCC          39
0055 #define JZ4780_CLK_AIC          40
0056 #define JZ4780_CLK_TSSI0        41
0057 #define JZ4780_CLK_OWI          42
0058 #define JZ4780_CLK_KBC          43
0059 #define JZ4780_CLK_SADC         44
0060 #define JZ4780_CLK_UART0        45
0061 #define JZ4780_CLK_UART1        46
0062 #define JZ4780_CLK_UART2        47
0063 #define JZ4780_CLK_UART3        48
0064 #define JZ4780_CLK_SSI1         49
0065 #define JZ4780_CLK_SSI2         50
0066 #define JZ4780_CLK_PDMA         51
0067 #define JZ4780_CLK_GPS          52
0068 #define JZ4780_CLK_MAC          53
0069 #define JZ4780_CLK_SMB2         54
0070 #define JZ4780_CLK_CIM          55
0071 #define JZ4780_CLK_LCD          56
0072 #define JZ4780_CLK_TVE          57
0073 #define JZ4780_CLK_IPU          58
0074 #define JZ4780_CLK_DDR0         59
0075 #define JZ4780_CLK_DDR1         60
0076 #define JZ4780_CLK_SMB3         61
0077 #define JZ4780_CLK_TSSI1        62
0078 #define JZ4780_CLK_COMPRESS     63
0079 #define JZ4780_CLK_AIC1         64
0080 #define JZ4780_CLK_GPVLC        65
0081 #define JZ4780_CLK_OTG1         66
0082 #define JZ4780_CLK_UART4        67
0083 #define JZ4780_CLK_AHBMON       68
0084 #define JZ4780_CLK_SMB4         69
0085 #define JZ4780_CLK_DES          70
0086 #define JZ4780_CLK_X2D          71
0087 #define JZ4780_CLK_CORE1        72
0088 #define JZ4780_CLK_EXCLK_DIV512 73
0089 #define JZ4780_CLK_RTC          74
0090
0091 #endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */