dt-bindings/clock/ingenic%2Cjz4760-cgu.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * This header provides clock numbers for the ingenic,jz4760-cgu DT binding.
0004  */
0005
0006 #ifndef __DT_BINDINGS_CLOCK_JZ4760_CGU_H__
0007 #define __DT_BINDINGS_CLOCK_JZ4760_CGU_H__
0008
0009 #define JZ4760_CLK_EXT      0
0010 #define JZ4760_CLK_OSC32K   1
0011 #define JZ4760_CLK_PLL0     2
0012 #define JZ4760_CLK_PLL0_HALF    3
0013 #define JZ4760_CLK_PLL1     4
0014 #define JZ4760_CLK_CCLK     5
0015 #define JZ4760_CLK_HCLK     6
0016 #define JZ4760_CLK_SCLK     7
0017 #define JZ4760_CLK_H2CLK    8
0018 #define JZ4760_CLK_MCLK     9
0019 #define JZ4760_CLK_PCLK     10
0020 #define JZ4760_CLK_MMC_MUX  11
0021 #define JZ4760_CLK_MMC0     12
0022 #define JZ4760_CLK_MMC1     13
0023 #define JZ4760_CLK_MMC2     14
0024 #define JZ4760_CLK_CIM      15
0025 #define JZ4760_CLK_UHC      16
0026 #define JZ4760_CLK_GPU      17
0027 #define JZ4760_CLK_GPS      18
0028 #define JZ4760_CLK_SSI_MUX  19
0029 #define JZ4760_CLK_PCM      20
0030 #define JZ4760_CLK_I2S      21
0031 #define JZ4760_CLK_OTG      22
0032 #define JZ4760_CLK_SSI0     23
0033 #define JZ4760_CLK_SSI1     24
0034 #define JZ4760_CLK_SSI2     25
0035 #define JZ4760_CLK_DMA      26
0036 #define JZ4760_CLK_I2C0     27
0037 #define JZ4760_CLK_I2C1     28
0038 #define JZ4760_CLK_UART0    29
0039 #define JZ4760_CLK_UART1    30
0040 #define JZ4760_CLK_UART2    31
0041 #define JZ4760_CLK_UART3    32
0042 #define JZ4760_CLK_IPU      33
0043 #define JZ4760_CLK_ADC      34
0044 #define JZ4760_CLK_AIC      35
0045 #define JZ4760_CLK_VPU      36
0046 #define JZ4760_CLK_UHC_PHY  37
0047 #define JZ4760_CLK_OTG_PHY  38
0048 #define JZ4760_CLK_EXT512   39
0049 #define JZ4760_CLK_RTC      40
0050 #define JZ4760_CLK_LPCLK_DIV    41
0051 #define JZ4760_CLK_TVE      42
0052 #define JZ4760_CLK_LPCLK    43
0053 #define JZ4760_CLK_MDMA     44
0054 #define JZ4760_CLK_BDMA     45
0055
0056 #endif /* __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ */