dt-bindings/clock/ingenic%2Cjz4740-cgu.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * This header provides clock numbers for the ingenic,jz4740-cgu DT binding.
0004  *
0005  * They are roughly ordered as:
0006  *   - external clocks
0007  *   - PLLs
0008  *   - muxes/dividers in the order they appear in the jz4740 programmers manual
0009  *   - gates in order of their bit in the CLKGR* registers
0010  */
0011
0012 #ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
0013 #define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
0014
0015 #define JZ4740_CLK_EXT      0
0016 #define JZ4740_CLK_RTC      1
0017 #define JZ4740_CLK_PLL      2
0018 #define JZ4740_CLK_PLL_HALF 3
0019 #define JZ4740_CLK_CCLK     4
0020 #define JZ4740_CLK_HCLK     5
0021 #define JZ4740_CLK_PCLK     6
0022 #define JZ4740_CLK_MCLK     7
0023 #define JZ4740_CLK_LCD      8
0024 #define JZ4740_CLK_LCD_PCLK 9
0025 #define JZ4740_CLK_I2S      10
0026 #define JZ4740_CLK_SPI      11
0027 #define JZ4740_CLK_MMC      12
0028 #define JZ4740_CLK_UHC      13
0029 #define JZ4740_CLK_UDC      14
0030 #define JZ4740_CLK_UART0    15
0031 #define JZ4740_CLK_UART1    16
0032 #define JZ4740_CLK_DMA      17
0033 #define JZ4740_CLK_IPU      18
0034 #define JZ4740_CLK_ADC      19
0035 #define JZ4740_CLK_I2C      20
0036 #define JZ4740_CLK_AIC      21
0037 #define JZ4740_CLK_TCU      22
0038
0039 #endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */