dt-bindings/clock/imxrt1050-clock.h

0001 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
0002 /*
0003  * Copyright(C) 2019
0004  * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
0005  */
0006
0007 #ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H
0008 #define __DT_BINDINGS_CLOCK_IMXRT1050_H
0009
0010 #define IMXRT1050_CLK_DUMMY         0
0011 #define IMXRT1050_CLK_CKIL          1
0012 #define IMXRT1050_CLK_CKIH          2
0013 #define IMXRT1050_CLK_OSC           3
0014 #define IMXRT1050_CLK_PLL2_PFD0_352M        4
0015 #define IMXRT1050_CLK_PLL2_PFD1_594M        5
0016 #define IMXRT1050_CLK_PLL2_PFD2_396M        6
0017 #define IMXRT1050_CLK_PLL3_PFD0_720M        7
0018 #define IMXRT1050_CLK_PLL3_PFD1_664_62M     8
0019 #define IMXRT1050_CLK_PLL3_PFD2_508_24M     9
0020 #define IMXRT1050_CLK_PLL3_PFD3_454_74M     10
0021 #define IMXRT1050_CLK_PLL2_198M         11
0022 #define IMXRT1050_CLK_PLL3_120M         12
0023 #define IMXRT1050_CLK_PLL3_80M          13
0024 #define IMXRT1050_CLK_PLL3_60M          14
0025 #define IMXRT1050_CLK_PLL1_BYPASS       15
0026 #define IMXRT1050_CLK_PLL2_BYPASS       16
0027 #define IMXRT1050_CLK_PLL3_BYPASS       17
0028 #define IMXRT1050_CLK_PLL5_BYPASS       19
0029 #define IMXRT1050_CLK_PLL1_REF_SEL      20
0030 #define IMXRT1050_CLK_PLL2_REF_SEL      21
0031 #define IMXRT1050_CLK_PLL3_REF_SEL      22
0032 #define IMXRT1050_CLK_PLL5_REF_SEL      23
0033 #define IMXRT1050_CLK_PRE_PERIPH_SEL        24
0034 #define IMXRT1050_CLK_PERIPH_SEL        25
0035 #define IMXRT1050_CLK_SEMC_ALT_SEL      26
0036 #define IMXRT1050_CLK_SEMC_SEL          27
0037 #define IMXRT1050_CLK_USDHC1_SEL        28
0038 #define IMXRT1050_CLK_USDHC2_SEL        29
0039 #define IMXRT1050_CLK_LPUART_SEL        30
0040 #define IMXRT1050_CLK_LCDIF_SEL         31
0041 #define IMXRT1050_CLK_VIDEO_POST_DIV_SEL    32
0042 #define IMXRT1050_CLK_VIDEO_DIV         33
0043 #define IMXRT1050_CLK_ARM_PODF          34
0044 #define IMXRT1050_CLK_LPUART_PODF       35
0045 #define IMXRT1050_CLK_USDHC1_PODF       36
0046 #define IMXRT1050_CLK_USDHC2_PODF       37
0047 #define IMXRT1050_CLK_SEMC_PODF         38
0048 #define IMXRT1050_CLK_AHB_PODF          39
0049 #define IMXRT1050_CLK_LCDIF_PRED        40
0050 #define IMXRT1050_CLK_LCDIF_PODF        41
0051 #define IMXRT1050_CLK_USDHC1            42
0052 #define IMXRT1050_CLK_USDHC2            43
0053 #define IMXRT1050_CLK_LPUART1           44
0054 #define IMXRT1050_CLK_SEMC          45
0055 #define IMXRT1050_CLK_LCDIF_APB         46
0056 #define IMXRT1050_CLK_PLL1_ARM          47
0057 #define IMXRT1050_CLK_PLL2_SYS          48
0058 #define IMXRT1050_CLK_PLL3_USB_OTG      49
0059 #define IMXRT1050_CLK_PLL4_AUDIO        50
0060 #define IMXRT1050_CLK_PLL5_VIDEO        51
0061 #define IMXRT1050_CLK_PLL6_ENET         52
0062 #define IMXRT1050_CLK_PLL7_USB_HOST     53
0063 #define IMXRT1050_CLK_LCDIF_PIX         54
0064 #define IMXRT1050_CLK_USBOH3            55
0065 #define IMXRT1050_CLK_IPG_PDOF          56
0066 #define IMXRT1050_CLK_PER_CLK_SEL       57
0067 #define IMXRT1050_CLK_PER_PDOF          58
0068 #define IMXRT1050_CLK_DMA           59
0069 #define IMXRT1050_CLK_DMA_MUX           60
0070 #define IMXRT1050_CLK_END           61
0071
0072 #endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */