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0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Copyright (C) 2016 Freescale Semiconductor, Inc.
0004  * Copyright 2017~2018 NXP
0005  *
0006  */
0007 
0008 #ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
0009 #define __DT_BINDINGS_CLOCK_IMX7ULP_H
0010 
0011 /* SCG1 */
0012 
0013 #define IMX7ULP_CLK_DUMMY       0
0014 #define IMX7ULP_CLK_ROSC        1
0015 #define IMX7ULP_CLK_SOSC        2
0016 #define IMX7ULP_CLK_FIRC        3
0017 #define IMX7ULP_CLK_SPLL_PRE_SEL    4
0018 #define IMX7ULP_CLK_SPLL_PRE_DIV    5
0019 #define IMX7ULP_CLK_SPLL        6
0020 #define IMX7ULP_CLK_SPLL_POST_DIV1  7
0021 #define IMX7ULP_CLK_SPLL_POST_DIV2  8
0022 #define IMX7ULP_CLK_SPLL_PFD0       9
0023 #define IMX7ULP_CLK_SPLL_PFD1       10
0024 #define IMX7ULP_CLK_SPLL_PFD2       11
0025 #define IMX7ULP_CLK_SPLL_PFD3       12
0026 #define IMX7ULP_CLK_SPLL_PFD_SEL    13
0027 #define IMX7ULP_CLK_SPLL_SEL        14
0028 #define IMX7ULP_CLK_APLL_PRE_SEL    15
0029 #define IMX7ULP_CLK_APLL_PRE_DIV    16
0030 #define IMX7ULP_CLK_APLL        17
0031 #define IMX7ULP_CLK_APLL_POST_DIV1  18
0032 #define IMX7ULP_CLK_APLL_POST_DIV2  19
0033 #define IMX7ULP_CLK_APLL_PFD0       20
0034 #define IMX7ULP_CLK_APLL_PFD1       21
0035 #define IMX7ULP_CLK_APLL_PFD2       22
0036 #define IMX7ULP_CLK_APLL_PFD3       23
0037 #define IMX7ULP_CLK_APLL_PFD_SEL    24
0038 #define IMX7ULP_CLK_APLL_SEL        25
0039 #define IMX7ULP_CLK_UPLL        26
0040 #define IMX7ULP_CLK_SYS_SEL     27
0041 #define IMX7ULP_CLK_CORE_DIV        28
0042 #define IMX7ULP_CLK_BUS_DIV     29
0043 #define IMX7ULP_CLK_PLAT_DIV        30
0044 #define IMX7ULP_CLK_DDR_SEL     31
0045 #define IMX7ULP_CLK_DDR_DIV     32
0046 #define IMX7ULP_CLK_NIC_SEL     33
0047 #define IMX7ULP_CLK_NIC0_DIV        34
0048 #define IMX7ULP_CLK_GPU_DIV     35
0049 #define IMX7ULP_CLK_NIC1_DIV        36
0050 #define IMX7ULP_CLK_NIC1_BUS_DIV    37
0051 #define IMX7ULP_CLK_NIC1_EXT_DIV    38
0052 /* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */
0053 #define IMX7ULP_CLK_MIPI_PLL        39
0054 #define IMX7ULP_CLK_SIRC        40
0055 #define IMX7ULP_CLK_SOSC_BUS_CLK    41
0056 #define IMX7ULP_CLK_FIRC_BUS_CLK    42
0057 #define IMX7ULP_CLK_SPLL_BUS_CLK    43
0058 #define IMX7ULP_CLK_HSRUN_SYS_SEL   44
0059 #define IMX7ULP_CLK_HSRUN_CORE_DIV  45
0060 
0061 #define IMX7ULP_CLK_CORE        46
0062 #define IMX7ULP_CLK_HSRUN_CORE      47
0063 
0064 #define IMX7ULP_CLK_SCG1_END        48
0065 
0066 /* PCC2 */
0067 #define IMX7ULP_CLK_DMA1        0
0068 #define IMX7ULP_CLK_RGPIO2P1        1
0069 #define IMX7ULP_CLK_FLEXBUS     2
0070 #define IMX7ULP_CLK_SEMA42_1        3
0071 #define IMX7ULP_CLK_DMA_MUX1        4
0072 #define IMX7ULP_CLK_CAAM        6
0073 #define IMX7ULP_CLK_LPTPM4      7
0074 #define IMX7ULP_CLK_LPTPM5      8
0075 #define IMX7ULP_CLK_LPIT1       9
0076 #define IMX7ULP_CLK_LPSPI2      10
0077 #define IMX7ULP_CLK_LPSPI3      11
0078 #define IMX7ULP_CLK_LPI2C4      12
0079 #define IMX7ULP_CLK_LPI2C5      13
0080 #define IMX7ULP_CLK_LPUART4     14
0081 #define IMX7ULP_CLK_LPUART5     15
0082 #define IMX7ULP_CLK_FLEXIO1     16
0083 #define IMX7ULP_CLK_USB0        17
0084 #define IMX7ULP_CLK_USB1        18
0085 #define IMX7ULP_CLK_USB_PHY     19
0086 #define IMX7ULP_CLK_USB_PL301       20
0087 #define IMX7ULP_CLK_USDHC0      21
0088 #define IMX7ULP_CLK_USDHC1      22
0089 #define IMX7ULP_CLK_WDG1        23
0090 #define IMX7ULP_CLK_WDG2        24
0091 
0092 #define IMX7ULP_CLK_PCC2_END        25
0093 
0094 /* PCC3 */
0095 #define IMX7ULP_CLK_LPTPM6      0
0096 #define IMX7ULP_CLK_LPTPM7      1
0097 #define IMX7ULP_CLK_LPI2C6      2
0098 #define IMX7ULP_CLK_LPI2C7      3
0099 #define IMX7ULP_CLK_LPUART6     4
0100 #define IMX7ULP_CLK_LPUART7     5
0101 #define IMX7ULP_CLK_VIU         6
0102 #define IMX7ULP_CLK_DSI         7
0103 #define IMX7ULP_CLK_LCDIF       8
0104 #define IMX7ULP_CLK_MMDC        9
0105 #define IMX7ULP_CLK_PCTLC       10
0106 #define IMX7ULP_CLK_PCTLD       11
0107 #define IMX7ULP_CLK_PCTLE       12
0108 #define IMX7ULP_CLK_PCTLF       13
0109 #define IMX7ULP_CLK_GPU3D       14
0110 #define IMX7ULP_CLK_GPU2D       15
0111 
0112 #define IMX7ULP_CLK_PCC3_END        16
0113 
0114 /* SMC1 */
0115 #define IMX7ULP_CLK_ARM         0
0116 
0117 #define IMX7ULP_CLK_SMC1_END        1
0118 
0119 #endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */