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0006 #ifndef __DT_BINDINGS_CLOCK_IMX27_H
0007 #define __DT_BINDINGS_CLOCK_IMX27_H
0008
0009 #define IMX27_CLK_DUMMY 0
0010 #define IMX27_CLK_CKIH 1
0011 #define IMX27_CLK_CKIL 2
0012 #define IMX27_CLK_MPLL 3
0013 #define IMX27_CLK_SPLL 4
0014 #define IMX27_CLK_MPLL_MAIN2 5
0015 #define IMX27_CLK_AHB 6
0016 #define IMX27_CLK_IPG 7
0017 #define IMX27_CLK_NFC_DIV 8
0018 #define IMX27_CLK_PER1_DIV 9
0019 #define IMX27_CLK_PER2_DIV 10
0020 #define IMX27_CLK_PER3_DIV 11
0021 #define IMX27_CLK_PER4_DIV 12
0022 #define IMX27_CLK_VPU_SEL 13
0023 #define IMX27_CLK_VPU_DIV 14
0024 #define IMX27_CLK_USB_DIV 15
0025 #define IMX27_CLK_CPU_SEL 16
0026 #define IMX27_CLK_CLKO_SEL 17
0027 #define IMX27_CLK_CPU_DIV 18
0028 #define IMX27_CLK_CLKO_DIV 19
0029 #define IMX27_CLK_SSI1_SEL 20
0030 #define IMX27_CLK_SSI2_SEL 21
0031 #define IMX27_CLK_SSI1_DIV 22
0032 #define IMX27_CLK_SSI2_DIV 23
0033 #define IMX27_CLK_CLKO_EN 24
0034 #define IMX27_CLK_SSI2_IPG_GATE 25
0035 #define IMX27_CLK_SSI1_IPG_GATE 26
0036 #define IMX27_CLK_SLCDC_IPG_GATE 27
0037 #define IMX27_CLK_SDHC3_IPG_GATE 28
0038 #define IMX27_CLK_SDHC2_IPG_GATE 29
0039 #define IMX27_CLK_SDHC1_IPG_GATE 30
0040 #define IMX27_CLK_SCC_IPG_GATE 31
0041 #define IMX27_CLK_SAHARA_IPG_GATE 32
0042 #define IMX27_CLK_RTC_IPG_GATE 33
0043 #define IMX27_CLK_PWM_IPG_GATE 34
0044 #define IMX27_CLK_OWIRE_IPG_GATE 35
0045 #define IMX27_CLK_LCDC_IPG_GATE 36
0046 #define IMX27_CLK_KPP_IPG_GATE 37
0047 #define IMX27_CLK_IIM_IPG_GATE 38
0048 #define IMX27_CLK_I2C2_IPG_GATE 39
0049 #define IMX27_CLK_I2C1_IPG_GATE 40
0050 #define IMX27_CLK_GPT6_IPG_GATE 41
0051 #define IMX27_CLK_GPT5_IPG_GATE 42
0052 #define IMX27_CLK_GPT4_IPG_GATE 43
0053 #define IMX27_CLK_GPT3_IPG_GATE 44
0054 #define IMX27_CLK_GPT2_IPG_GATE 45
0055 #define IMX27_CLK_GPT1_IPG_GATE 46
0056 #define IMX27_CLK_GPIO_IPG_GATE 47
0057 #define IMX27_CLK_FEC_IPG_GATE 48
0058 #define IMX27_CLK_EMMA_IPG_GATE 49
0059 #define IMX27_CLK_DMA_IPG_GATE 50
0060 #define IMX27_CLK_CSPI3_IPG_GATE 51
0061 #define IMX27_CLK_CSPI2_IPG_GATE 52
0062 #define IMX27_CLK_CSPI1_IPG_GATE 53
0063 #define IMX27_CLK_NFC_BAUD_GATE 54
0064 #define IMX27_CLK_SSI2_BAUD_GATE 55
0065 #define IMX27_CLK_SSI1_BAUD_GATE 56
0066 #define IMX27_CLK_VPU_BAUD_GATE 57
0067 #define IMX27_CLK_PER4_GATE 58
0068 #define IMX27_CLK_PER3_GATE 59
0069 #define IMX27_CLK_PER2_GATE 60
0070 #define IMX27_CLK_PER1_GATE 61
0071 #define IMX27_CLK_USB_AHB_GATE 62
0072 #define IMX27_CLK_SLCDC_AHB_GATE 63
0073 #define IMX27_CLK_SAHARA_AHB_GATE 64
0074 #define IMX27_CLK_LCDC_AHB_GATE 65
0075 #define IMX27_CLK_VPU_AHB_GATE 66
0076 #define IMX27_CLK_FEC_AHB_GATE 67
0077 #define IMX27_CLK_EMMA_AHB_GATE 68
0078 #define IMX27_CLK_EMI_AHB_GATE 69
0079 #define IMX27_CLK_DMA_AHB_GATE 70
0080 #define IMX27_CLK_CSI_AHB_GATE 71
0081 #define IMX27_CLK_BROM_AHB_GATE 72
0082 #define IMX27_CLK_ATA_AHB_GATE 73
0083 #define IMX27_CLK_WDOG_IPG_GATE 74
0084 #define IMX27_CLK_USB_IPG_GATE 75
0085 #define IMX27_CLK_UART6_IPG_GATE 76
0086 #define IMX27_CLK_UART5_IPG_GATE 77
0087 #define IMX27_CLK_UART4_IPG_GATE 78
0088 #define IMX27_CLK_UART3_IPG_GATE 79
0089 #define IMX27_CLK_UART2_IPG_GATE 80
0090 #define IMX27_CLK_UART1_IPG_GATE 81
0091 #define IMX27_CLK_CKIH_DIV1P5 82
0092 #define IMX27_CLK_FPM 83
0093 #define IMX27_CLK_MPLL_OSC_SEL 84
0094 #define IMX27_CLK_MPLL_SEL 85
0095 #define IMX27_CLK_SPLL_GATE 86
0096 #define IMX27_CLK_MSHC_DIV 87
0097 #define IMX27_CLK_RTIC_IPG_GATE 88
0098 #define IMX27_CLK_MSHC_IPG_GATE 89
0099 #define IMX27_CLK_RTIC_AHB_GATE 90
0100 #define IMX27_CLK_MSHC_BAUD_GATE 91
0101 #define IMX27_CLK_CKIH_GATE 92
0102 #define IMX27_CLK_MAX 93
0103
0104 #endif
