dt-bindings/clock/imx21-clock.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
0004  */
0005
0006 #ifndef __DT_BINDINGS_CLOCK_IMX21_H
0007 #define __DT_BINDINGS_CLOCK_IMX21_H
0008
0009 #define IMX21_CLK_DUMMY         0
0010 #define IMX21_CLK_CKIL          1
0011 #define IMX21_CLK_CKIH          2
0012 #define IMX21_CLK_FPM           3
0013 #define IMX21_CLK_CKIH_DIV1P5       4
0014 #define IMX21_CLK_MPLL_GATE     5
0015 #define IMX21_CLK_SPLL_GATE     6
0016 #define IMX21_CLK_FPM_GATE      7
0017 #define IMX21_CLK_CKIH_GATE     8
0018 #define IMX21_CLK_MPLL_OSC_SEL      9
0019 #define IMX21_CLK_IPG           10
0020 #define IMX21_CLK_HCLK          11
0021 #define IMX21_CLK_MPLL_SEL      12
0022 #define IMX21_CLK_SPLL_SEL      13
0023 #define IMX21_CLK_SSI1_SEL      14
0024 #define IMX21_CLK_SSI2_SEL      15
0025 #define IMX21_CLK_USB_DIV       16
0026 #define IMX21_CLK_FCLK          17
0027 #define IMX21_CLK_MPLL          18
0028 #define IMX21_CLK_SPLL          19
0029 #define IMX21_CLK_NFC_DIV       20
0030 #define IMX21_CLK_SSI1_DIV      21
0031 #define IMX21_CLK_SSI2_DIV      22
0032 #define IMX21_CLK_PER1          23
0033 #define IMX21_CLK_PER2          24
0034 #define IMX21_CLK_PER3          25
0035 #define IMX21_CLK_PER4          26
0036 #define IMX21_CLK_UART1_IPG_GATE    27
0037 #define IMX21_CLK_UART2_IPG_GATE    28
0038 #define IMX21_CLK_UART3_IPG_GATE    29
0039 #define IMX21_CLK_UART4_IPG_GATE    30
0040 #define IMX21_CLK_CSPI1_IPG_GATE    31
0041 #define IMX21_CLK_CSPI2_IPG_GATE    32
0042 #define IMX21_CLK_SSI1_GATE     33
0043 #define IMX21_CLK_SSI2_GATE     34
0044 #define IMX21_CLK_SDHC1_IPG_GATE    35
0045 #define IMX21_CLK_SDHC2_IPG_GATE    36
0046 #define IMX21_CLK_GPIO_GATE     37
0047 #define IMX21_CLK_I2C_GATE      38
0048 #define IMX21_CLK_DMA_GATE      39
0049 #define IMX21_CLK_USB_GATE      40
0050 #define IMX21_CLK_EMMA_GATE     41
0051 #define IMX21_CLK_SSI2_BAUD_GATE    42
0052 #define IMX21_CLK_SSI1_BAUD_GATE    43
0053 #define IMX21_CLK_LCDC_IPG_GATE     44
0054 #define IMX21_CLK_NFC_GATE      45
0055 #define IMX21_CLK_LCDC_HCLK_GATE    46
0056 #define IMX21_CLK_PER4_GATE     47
0057 #define IMX21_CLK_BMI_GATE      48
0058 #define IMX21_CLK_USB_HCLK_GATE     49
0059 #define IMX21_CLK_SLCDC_GATE        50
0060 #define IMX21_CLK_SLCDC_HCLK_GATE   51
0061 #define IMX21_CLK_EMMA_HCLK_GATE    52
0062 #define IMX21_CLK_BROM_GATE     53
0063 #define IMX21_CLK_DMA_HCLK_GATE     54
0064 #define IMX21_CLK_CSI_HCLK_GATE     55
0065 #define IMX21_CLK_CSPI3_IPG_GATE    56
0066 #define IMX21_CLK_WDOG_GATE     57
0067 #define IMX21_CLK_GPT1_IPG_GATE     58
0068 #define IMX21_CLK_GPT2_IPG_GATE     59
0069 #define IMX21_CLK_GPT3_IPG_GATE     60
0070 #define IMX21_CLK_PWM_IPG_GATE      61
0071 #define IMX21_CLK_RTC_GATE      62
0072 #define IMX21_CLK_KPP_GATE      63
0073 #define IMX21_CLK_OWIRE_GATE        64
0074 #define IMX21_CLK_MAX           65
0075
0076 #endif