dt-bindings/clock/imx1-clock.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
0004  */
0005
0006 #ifndef __DT_BINDINGS_CLOCK_IMX1_H
0007 #define __DT_BINDINGS_CLOCK_IMX1_H
0008
0009 #define IMX1_CLK_DUMMY      0
0010 #define IMX1_CLK_CLK32      1
0011 #define IMX1_CLK_CLK16M_EXT 2
0012 #define IMX1_CLK_CLK16M     3
0013 #define IMX1_CLK_CLK32_PREMULT  4
0014 #define IMX1_CLK_PREM       5
0015 #define IMX1_CLK_MPLL       6
0016 #define IMX1_CLK_MPLL_GATE  7
0017 #define IMX1_CLK_SPLL       8
0018 #define IMX1_CLK_SPLL_GATE  9
0019 #define IMX1_CLK_MCU        10
0020 #define IMX1_CLK_FCLK       11
0021 #define IMX1_CLK_HCLK       12
0022 #define IMX1_CLK_CLK48M     13
0023 #define IMX1_CLK_PER1       14
0024 #define IMX1_CLK_PER2       15
0025 #define IMX1_CLK_PER3       16
0026 #define IMX1_CLK_CLKO       17
0027 #define IMX1_CLK_UART3_GATE 18
0028 #define IMX1_CLK_SSI2_GATE  19
0029 #define IMX1_CLK_BROM_GATE  20
0030 #define IMX1_CLK_DMA_GATE   21
0031 #define IMX1_CLK_CSI_GATE   22
0032 #define IMX1_CLK_MMA_GATE   23
0033 #define IMX1_CLK_USBD_GATE  24
0034 #define IMX1_CLK_MAX        25
0035
0036 #endif