dt-bindings/clock/hix5hd2-clock.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2014 Linaro Ltd.
0004  * Copyright (c) 2014 Hisilicon Limited.
0005  */
0006
0007 #ifndef __DTS_HIX5HD2_CLOCK_H
0008 #define __DTS_HIX5HD2_CLOCK_H
0009
0010 /* fixed rate */
0011 #define HIX5HD2_FIXED_1200M     1
0012 #define HIX5HD2_FIXED_400M      2
0013 #define HIX5HD2_FIXED_48M       3
0014 #define HIX5HD2_FIXED_24M       4
0015 #define HIX5HD2_FIXED_600M      5
0016 #define HIX5HD2_FIXED_300M      6
0017 #define HIX5HD2_FIXED_75M       7
0018 #define HIX5HD2_FIXED_200M      8
0019 #define HIX5HD2_FIXED_100M      9
0020 #define HIX5HD2_FIXED_40M       10
0021 #define HIX5HD2_FIXED_150M      11
0022 #define HIX5HD2_FIXED_1728M     12
0023 #define HIX5HD2_FIXED_28P8M     13
0024 #define HIX5HD2_FIXED_432M      14
0025 #define HIX5HD2_FIXED_345P6M        15
0026 #define HIX5HD2_FIXED_288M      16
0027 #define HIX5HD2_FIXED_60M       17
0028 #define HIX5HD2_FIXED_750M      18
0029 #define HIX5HD2_FIXED_500M      19
0030 #define HIX5HD2_FIXED_54M       20
0031 #define HIX5HD2_FIXED_27M       21
0032 #define HIX5HD2_FIXED_1500M     22
0033 #define HIX5HD2_FIXED_375M      23
0034 #define HIX5HD2_FIXED_187M      24
0035 #define HIX5HD2_FIXED_250M      25
0036 #define HIX5HD2_FIXED_125M      26
0037 #define HIX5HD2_FIXED_2P02M     27
0038 #define HIX5HD2_FIXED_50M       28
0039 #define HIX5HD2_FIXED_25M       29
0040 #define HIX5HD2_FIXED_83M       30
0041
0042 /* mux clocks */
0043 #define HIX5HD2_SFC_MUX         64
0044 #define HIX5HD2_MMC_MUX         65
0045 #define HIX5HD2_FEPHY_MUX       66
0046 #define HIX5HD2_SD_MUX          67
0047
0048 /* gate clocks */
0049 #define HIX5HD2_SFC_RST         128
0050 #define HIX5HD2_SFC_CLK         129
0051 #define HIX5HD2_MMC_CIU_CLK     130
0052 #define HIX5HD2_MMC_BIU_CLK     131
0053 #define HIX5HD2_MMC_CIU_RST     132
0054 #define HIX5HD2_FWD_BUS_CLK     133
0055 #define HIX5HD2_FWD_SYS_CLK     134
0056 #define HIX5HD2_MAC0_PHY_CLK        135
0057 #define HIX5HD2_SD_CIU_CLK      136
0058 #define HIX5HD2_SD_BIU_CLK      137
0059 #define HIX5HD2_SD_CIU_RST      138
0060 #define HIX5HD2_WDG0_CLK        139
0061 #define HIX5HD2_WDG0_RST        140
0062 #define HIX5HD2_I2C0_CLK        141
0063 #define HIX5HD2_I2C0_RST        142
0064 #define HIX5HD2_I2C1_CLK        143
0065 #define HIX5HD2_I2C1_RST        144
0066 #define HIX5HD2_I2C2_CLK        145
0067 #define HIX5HD2_I2C2_RST        146
0068 #define HIX5HD2_I2C3_CLK        147
0069 #define HIX5HD2_I2C3_RST        148
0070 #define HIX5HD2_I2C4_CLK        149
0071 #define HIX5HD2_I2C4_RST        150
0072 #define HIX5HD2_I2C5_CLK        151
0073 #define HIX5HD2_I2C5_RST        152
0074
0075 /* complex */
0076 #define HIX5HD2_MAC0_CLK        192
0077 #define HIX5HD2_MAC1_CLK        193
0078 #define HIX5HD2_SATA_CLK        194
0079 #define HIX5HD2_USB_CLK         195
0080
0081 #define HIX5HD2_NR_CLKS         256
0082 #endif  /* __DTS_HIX5HD2_CLOCK_H */