dt-bindings/clock/hi3516cv300-clock.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
0004  */
0005
0006 #ifndef __DTS_HI3516CV300_CLOCK_H
0007 #define __DTS_HI3516CV300_CLOCK_H
0008
0009 /* hi3516CV300 core CRG */
0010 #define HI3516CV300_APB_CLK     0
0011 #define HI3516CV300_UART0_CLK       1
0012 #define HI3516CV300_UART1_CLK       2
0013 #define HI3516CV300_UART2_CLK       3
0014 #define HI3516CV300_SPI0_CLK        4
0015 #define HI3516CV300_SPI1_CLK        5
0016 #define HI3516CV300_FMC_CLK     6
0017 #define HI3516CV300_MMC0_CLK        7
0018 #define HI3516CV300_MMC1_CLK        8
0019 #define HI3516CV300_MMC2_CLK        9
0020 #define HI3516CV300_MMC3_CLK        10
0021 #define HI3516CV300_ETH_CLK     11
0022 #define HI3516CV300_ETH_MACIF_CLK   12
0023 #define HI3516CV300_DMAC_CLK        13
0024 #define HI3516CV300_PWM_CLK     14
0025 #define HI3516CV300_USB2_BUS_CLK    15
0026 #define HI3516CV300_USB2_OHCI48M_CLK    16
0027 #define HI3516CV300_USB2_OHCI12M_CLK    17
0028 #define HI3516CV300_USB2_OTG_UTMI_CLK   18
0029 #define HI3516CV300_USB2_HST_PHY_CLK    19
0030 #define HI3516CV300_USB2_UTMI0_CLK  20
0031 #define HI3516CV300_USB2_PHY_CLK    21
0032
0033 /* hi3516CV300 sysctrl CRG */
0034 #define HI3516CV300_WDT_CLK     1
0035
0036 #endif  /* __DTS_HI3516CV300_CLOCK_H */