dt-bindings/clock/exynos5410.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
0004  * Copyright (c) 2016 Krzysztof Kozlowski
0005  *
0006  * Device Tree binding constants for Exynos5421 clock controller.
0007  */
0008
0009 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
0010 #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
0011
0012 /* core clocks */
0013 #define CLK_FIN_PLL     1
0014 #define CLK_FOUT_APLL       2
0015 #define CLK_FOUT_CPLL       3
0016 #define CLK_FOUT_MPLL       4
0017 #define CLK_FOUT_BPLL       5
0018 #define CLK_FOUT_KPLL       6
0019 #define CLK_FOUT_EPLL       7
0020
0021 /* gate for special clocks (sclk) */
0022 #define CLK_SCLK_UART0      128
0023 #define CLK_SCLK_UART1      129
0024 #define CLK_SCLK_UART2      130
0025 #define CLK_SCLK_UART3      131
0026 #define CLK_SCLK_MMC0       132
0027 #define CLK_SCLK_MMC1       133
0028 #define CLK_SCLK_MMC2       134
0029 #define CLK_SCLK_USBD300    150
0030 #define CLK_SCLK_USBD301    151
0031 #define CLK_SCLK_USBPHY300  152
0032 #define CLK_SCLK_USBPHY301  153
0033 #define CLK_SCLK_PWM        155
0034
0035 /* gate clocks */
0036 #define CLK_UART0       257
0037 #define CLK_UART1       258
0038 #define CLK_UART2       259
0039 #define CLK_UART3       260
0040 #define CLK_I2C0        261
0041 #define CLK_I2C1        262
0042 #define CLK_I2C2        263
0043 #define CLK_I2C3        264
0044 #define CLK_USI0        265
0045 #define CLK_USI1        266
0046 #define CLK_USI2        267
0047 #define CLK_USI3        268
0048 #define CLK_TSADC       270
0049 #define CLK_PWM         279
0050 #define CLK_MCT         315
0051 #define CLK_WDT         316
0052 #define CLK_RTC         317
0053 #define CLK_TMU         318
0054 #define CLK_MMC0        351
0055 #define CLK_MMC1        352
0056 #define CLK_MMC2        353
0057 #define CLK_PDMA0       362
0058 #define CLK_PDMA1       363
0059 #define CLK_USBH20      365
0060 #define CLK_USBD300     366
0061 #define CLK_USBD301     367
0062 #define CLK_SSS         471
0063
0064 #define CLK_NR_CLKS     512
0065
0066 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */