dt-bindings/clock/dra7.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright 2017 Texas Instruments, Inc.
0004  */
0005 #ifndef __DT_BINDINGS_CLK_DRA7_H
0006 #define __DT_BINDINGS_CLK_DRA7_H
0007
0008 #define DRA7_CLKCTRL_OFFSET 0x20
0009 #define DRA7_CLKCTRL_INDEX(offset)  ((offset) - DRA7_CLKCTRL_OFFSET)
0010
0011 /* mpu clocks */
0012 #define DRA7_MPU_MPU_CLKCTRL    DRA7_CLKCTRL_INDEX(0x20)
0013
0014 /* dsp1 clocks */
0015 #define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
0016
0017 /* ipu1 clocks */
0018 #define DRA7_IPU1_MMU_IPU1_CLKCTRL  DRA7_CLKCTRL_INDEX(0x20)
0019
0020 /* ipu clocks */
0021 #define DRA7_IPU_CLKCTRL_OFFSET 0x50
0022 #define DRA7_IPU_CLKCTRL_INDEX(offset)  ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
0023 #define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
0024 #define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
0025 #define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
0026 #define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
0027 #define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
0028 #define DRA7_IPU_I2C5_CLKCTRL   DRA7_IPU_CLKCTRL_INDEX(0x78)
0029 #define DRA7_IPU_UART6_CLKCTRL  DRA7_IPU_CLKCTRL_INDEX(0x80)
0030
0031 /* dsp2 clocks */
0032 #define DRA7_DSP2_MMU0_DSP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
0033
0034 /* rtc clocks */
0035 #define DRA7_RTC_RTCSS_CLKCTRL  DRA7_CLKCTRL_INDEX(0x44)
0036
0037 /* vip clocks */
0038 #define DRA7_CAM_VIP1_CLKCTRL   DRA7_CLKCTRL_INDEX(0x20)
0039 #define DRA7_CAM_VIP2_CLKCTRL   DRA7_CLKCTRL_INDEX(0x28)
0040 #define DRA7_CAM_VIP3_CLKCTRL   DRA7_CLKCTRL_INDEX(0x30)
0041
0042 /* vpe clocks */
0043 #define DRA7_VPE_CLKCTRL_OFFSET 0x60
0044 #define DRA7_VPE_CLKCTRL_INDEX(offset)  ((offset) - DRA7_VPE_CLKCTRL_OFFSET)
0045 #define DRA7_VPE_VPE_CLKCTRL    DRA7_VPE_CLKCTRL_INDEX(0x64)
0046
0047 /* coreaon clocks */
0048 #define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL    DRA7_CLKCTRL_INDEX(0x28)
0049 #define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL   DRA7_CLKCTRL_INDEX(0x38)
0050
0051 /* l3main1 clocks */
0052 #define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL  DRA7_CLKCTRL_INDEX(0x20)
0053 #define DRA7_L3MAIN1_GPMC_CLKCTRL   DRA7_CLKCTRL_INDEX(0x28)
0054 #define DRA7_L3MAIN1_TPCC_CLKCTRL   DRA7_CLKCTRL_INDEX(0x70)
0055 #define DRA7_L3MAIN1_TPTC0_CLKCTRL  DRA7_CLKCTRL_INDEX(0x78)
0056 #define DRA7_L3MAIN1_TPTC1_CLKCTRL  DRA7_CLKCTRL_INDEX(0x80)
0057 #define DRA7_L3MAIN1_VCP1_CLKCTRL   DRA7_CLKCTRL_INDEX(0x88)
0058 #define DRA7_L3MAIN1_VCP2_CLKCTRL   DRA7_CLKCTRL_INDEX(0x90)
0059
0060 /* ipu2 clocks */
0061 #define DRA7_IPU2_MMU_IPU2_CLKCTRL  DRA7_CLKCTRL_INDEX(0x20)
0062
0063 /* dma clocks */
0064 #define DRA7_DMA_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
0065
0066 /* emif clocks */
0067 #define DRA7_EMIF_DMM_CLKCTRL   DRA7_CLKCTRL_INDEX(0x20)
0068
0069 /* atl clocks */
0070 #define DRA7_ATL_CLKCTRL_OFFSET 0x0
0071 #define DRA7_ATL_CLKCTRL_INDEX(offset)  ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
0072 #define DRA7_ATL_ATL_CLKCTRL    DRA7_ATL_CLKCTRL_INDEX(0x0)
0073
0074 /* l4cfg clocks */
0075 #define DRA7_L4CFG_L4_CFG_CLKCTRL   DRA7_CLKCTRL_INDEX(0x20)
0076 #define DRA7_L4CFG_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
0077 #define DRA7_L4CFG_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
0078 #define DRA7_L4CFG_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
0079 #define DRA7_L4CFG_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
0080 #define DRA7_L4CFG_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58)
0081 #define DRA7_L4CFG_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60)
0082 #define DRA7_L4CFG_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68)
0083 #define DRA7_L4CFG_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
0084 #define DRA7_L4CFG_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
0085 #define DRA7_L4CFG_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
0086 #define DRA7_L4CFG_MAILBOX10_CLKCTRL    DRA7_CLKCTRL_INDEX(0x88)
0087 #define DRA7_L4CFG_MAILBOX11_CLKCTRL    DRA7_CLKCTRL_INDEX(0x90)
0088 #define DRA7_L4CFG_MAILBOX12_CLKCTRL    DRA7_CLKCTRL_INDEX(0x98)
0089 #define DRA7_L4CFG_MAILBOX13_CLKCTRL    DRA7_CLKCTRL_INDEX(0xa0)
0090
0091 /* l3instr clocks */
0092 #define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL  DRA7_CLKCTRL_INDEX(0x20)
0093 #define DRA7_L3INSTR_L3_INSTR_CLKCTRL   DRA7_CLKCTRL_INDEX(0x28)
0094
0095 /* iva clocks */
0096 #define DRA7_IVA_CLKCTRL        DRA7_CLKCTRL_INDEX(0x20)
0097 #define DRA7_SL2IF_CLKCTRL      DRA7_CLKCTRL_INDEX(0x28)
0098
0099 /* dss clocks */
0100 #define DRA7_DSS_DSS_CORE_CLKCTRL   DRA7_CLKCTRL_INDEX(0x20)
0101 #define DRA7_DSS_BB2D_CLKCTRL   DRA7_CLKCTRL_INDEX(0x30)
0102
0103 /* gpu clocks */
0104 #define DRA7_GPU_CLKCTRL        DRA7_CLKCTRL_INDEX(0x20)
0105
0106 /* l3init clocks */
0107 #define DRA7_L3INIT_MMC1_CLKCTRL    DRA7_CLKCTRL_INDEX(0x28)
0108 #define DRA7_L3INIT_MMC2_CLKCTRL    DRA7_CLKCTRL_INDEX(0x30)
0109 #define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
0110 #define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
0111 #define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
0112 #define DRA7_L3INIT_SATA_CLKCTRL    DRA7_CLKCTRL_INDEX(0x88)
0113 #define DRA7_L3INIT_OCP2SCP1_CLKCTRL    DRA7_CLKCTRL_INDEX(0xe0)
0114 #define DRA7_L3INIT_OCP2SCP3_CLKCTRL    DRA7_CLKCTRL_INDEX(0xe8)
0115 #define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
0116
0117 /* pcie clocks */
0118 #define DRA7_PCIE_CLKCTRL_OFFSET    0xb0
0119 #define DRA7_PCIE_CLKCTRL_INDEX(offset) ((offset) - DRA7_PCIE_CLKCTRL_OFFSET)
0120 #define DRA7_PCIE_PCIE1_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb0)
0121 #define DRA7_PCIE_PCIE2_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb8)
0122
0123 /* gmac clocks */
0124 #define DRA7_GMAC_CLKCTRL_OFFSET    0xd0
0125 #define DRA7_GMAC_CLKCTRL_INDEX(offset) ((offset) - DRA7_GMAC_CLKCTRL_OFFSET)
0126 #define DRA7_GMAC_GMAC_CLKCTRL  DRA7_GMAC_CLKCTRL_INDEX(0xd0)
0127
0128 /* l4per clocks */
0129 #define DRA7_L4PER_CLKCTRL_OFFSET   0x28
0130 #define DRA7_L4PER_CLKCTRL_INDEX(offset)    ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
0131 #define DRA7_L4PER_TIMER10_CLKCTRL  DRA7_L4PER_CLKCTRL_INDEX(0x28)
0132 #define DRA7_L4PER_TIMER11_CLKCTRL  DRA7_L4PER_CLKCTRL_INDEX(0x30)
0133 #define DRA7_L4PER_TIMER2_CLKCTRL   DRA7_L4PER_CLKCTRL_INDEX(0x38)
0134 #define DRA7_L4PER_TIMER3_CLKCTRL   DRA7_L4PER_CLKCTRL_INDEX(0x40)
0135 #define DRA7_L4PER_TIMER4_CLKCTRL   DRA7_L4PER_CLKCTRL_INDEX(0x48)
0136 #define DRA7_L4PER_TIMER9_CLKCTRL   DRA7_L4PER_CLKCTRL_INDEX(0x50)
0137 #define DRA7_L4PER_ELM_CLKCTRL  DRA7_L4PER_CLKCTRL_INDEX(0x58)
0138 #define DRA7_L4PER_GPIO2_CLKCTRL    DRA7_L4PER_CLKCTRL_INDEX(0x60)
0139 #define DRA7_L4PER_GPIO3_CLKCTRL    DRA7_L4PER_CLKCTRL_INDEX(0x68)
0140 #define DRA7_L4PER_GPIO4_CLKCTRL    DRA7_L4PER_CLKCTRL_INDEX(0x70)
0141 #define DRA7_L4PER_GPIO5_CLKCTRL    DRA7_L4PER_CLKCTRL_INDEX(0x78)
0142 #define DRA7_L4PER_GPIO6_CLKCTRL    DRA7_L4PER_CLKCTRL_INDEX(0x80)
0143 #define DRA7_L4PER_HDQ1W_CLKCTRL    DRA7_L4PER_CLKCTRL_INDEX(0x88)
0144 #define DRA7_L4PER_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
0145 #define DRA7_L4PER_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
0146 #define DRA7_L4PER_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
0147 #define DRA7_L4PER_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
0148 #define DRA7_L4PER_L4_PER1_CLKCTRL  DRA7_L4PER_CLKCTRL_INDEX(0xc0)
0149 #define DRA7_L4PER_MCSPI1_CLKCTRL   DRA7_L4PER_CLKCTRL_INDEX(0xf0)
0150 #define DRA7_L4PER_MCSPI2_CLKCTRL   DRA7_L4PER_CLKCTRL_INDEX(0xf8)
0151 #define DRA7_L4PER_MCSPI3_CLKCTRL   DRA7_L4PER_CLKCTRL_INDEX(0x100)
0152 #define DRA7_L4PER_MCSPI4_CLKCTRL   DRA7_L4PER_CLKCTRL_INDEX(0x108)
0153 #define DRA7_L4PER_GPIO7_CLKCTRL    DRA7_L4PER_CLKCTRL_INDEX(0x110)
0154 #define DRA7_L4PER_GPIO8_CLKCTRL    DRA7_L4PER_CLKCTRL_INDEX(0x118)
0155 #define DRA7_L4PER_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
0156 #define DRA7_L4PER_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
0157 #define DRA7_L4PER_UART1_CLKCTRL    DRA7_L4PER_CLKCTRL_INDEX(0x140)
0158 #define DRA7_L4PER_UART2_CLKCTRL    DRA7_L4PER_CLKCTRL_INDEX(0x148)
0159 #define DRA7_L4PER_UART3_CLKCTRL    DRA7_L4PER_CLKCTRL_INDEX(0x150)
0160 #define DRA7_L4PER_UART4_CLKCTRL    DRA7_L4PER_CLKCTRL_INDEX(0x158)
0161 #define DRA7_L4PER_UART5_CLKCTRL    DRA7_L4PER_CLKCTRL_INDEX(0x170)
0162
0163 /* l4sec clocks */
0164 #define DRA7_L4SEC_CLKCTRL_OFFSET   0x1a0
0165 #define DRA7_L4SEC_CLKCTRL_INDEX(offset)    ((offset) - DRA7_L4SEC_CLKCTRL_OFFSET)
0166 #define DRA7_L4SEC_AES1_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a0)
0167 #define DRA7_L4SEC_AES2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a8)
0168 #define DRA7_L4SEC_DES_CLKCTRL  DRA7_L4SEC_CLKCTRL_INDEX(0x1b0)
0169 #define DRA7_L4SEC_RNG_CLKCTRL  DRA7_L4SEC_CLKCTRL_INDEX(0x1c0)
0170 #define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8)
0171 #define DRA7_L4SEC_SHAM2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1f8)
0172
0173 /* l4per2 clocks */
0174 #define DRA7_L4PER2_CLKCTRL_OFFSET  0xc
0175 #define DRA7_L4PER2_CLKCTRL_INDEX(offset)   ((offset) - DRA7_L4PER2_CLKCTRL_OFFSET)
0176 #define DRA7_L4PER2_L4_PER2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc)
0177 #define DRA7_L4PER2_PRUSS1_CLKCTRL  DRA7_L4PER2_CLKCTRL_INDEX(0x18)
0178 #define DRA7_L4PER2_PRUSS2_CLKCTRL  DRA7_L4PER2_CLKCTRL_INDEX(0x20)
0179 #define DRA7_L4PER2_EPWMSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x90)
0180 #define DRA7_L4PER2_EPWMSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x98)
0181 #define DRA7_L4PER2_EPWMSS0_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc4)
0182 #define DRA7_L4PER2_QSPI_CLKCTRL    DRA7_L4PER2_CLKCTRL_INDEX(0x138)
0183 #define DRA7_L4PER2_MCASP2_CLKCTRL  DRA7_L4PER2_CLKCTRL_INDEX(0x160)
0184 #define DRA7_L4PER2_MCASP3_CLKCTRL  DRA7_L4PER2_CLKCTRL_INDEX(0x168)
0185 #define DRA7_L4PER2_MCASP5_CLKCTRL  DRA7_L4PER2_CLKCTRL_INDEX(0x178)
0186 #define DRA7_L4PER2_MCASP8_CLKCTRL  DRA7_L4PER2_CLKCTRL_INDEX(0x190)
0187 #define DRA7_L4PER2_MCASP4_CLKCTRL  DRA7_L4PER2_CLKCTRL_INDEX(0x198)
0188 #define DRA7_L4PER2_UART7_CLKCTRL   DRA7_L4PER2_CLKCTRL_INDEX(0x1d0)
0189 #define DRA7_L4PER2_UART8_CLKCTRL   DRA7_L4PER2_CLKCTRL_INDEX(0x1e0)
0190 #define DRA7_L4PER2_UART9_CLKCTRL   DRA7_L4PER2_CLKCTRL_INDEX(0x1e8)
0191 #define DRA7_L4PER2_DCAN2_CLKCTRL   DRA7_L4PER2_CLKCTRL_INDEX(0x1f0)
0192 #define DRA7_L4PER2_MCASP6_CLKCTRL  DRA7_L4PER2_CLKCTRL_INDEX(0x204)
0193 #define DRA7_L4PER2_MCASP7_CLKCTRL  DRA7_L4PER2_CLKCTRL_INDEX(0x208)
0194
0195 /* l4per3 clocks */
0196 #define DRA7_L4PER3_CLKCTRL_OFFSET  0x14
0197 #define DRA7_L4PER3_CLKCTRL_INDEX(offset)   ((offset) - DRA7_L4PER3_CLKCTRL_OFFSET)
0198 #define DRA7_L4PER3_L4_PER3_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x14)
0199 #define DRA7_L4PER3_TIMER13_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xc8)
0200 #define DRA7_L4PER3_TIMER14_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd0)
0201 #define DRA7_L4PER3_TIMER15_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd8)
0202 #define DRA7_L4PER3_TIMER16_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x130)
0203
0204 /* wkupaon clocks */
0205 #define DRA7_WKUPAON_L4_WKUP_CLKCTRL    DRA7_CLKCTRL_INDEX(0x20)
0206 #define DRA7_WKUPAON_WD_TIMER2_CLKCTRL  DRA7_CLKCTRL_INDEX(0x30)
0207 #define DRA7_WKUPAON_GPIO1_CLKCTRL  DRA7_CLKCTRL_INDEX(0x38)
0208 #define DRA7_WKUPAON_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
0209 #define DRA7_WKUPAON_TIMER12_CLKCTRL    DRA7_CLKCTRL_INDEX(0x48)
0210 #define DRA7_WKUPAON_COUNTER_32K_CLKCTRL    DRA7_CLKCTRL_INDEX(0x50)
0211 #define DRA7_WKUPAON_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
0212 #define DRA7_WKUPAON_DCAN1_CLKCTRL  DRA7_CLKCTRL_INDEX(0x88)
0213 #define DRA7_WKUPAON_ADC_CLKCTRL    DRA7_CLKCTRL_INDEX(0xa0)
0214
0215 #endif