dt-bindings/clock/bcm-ns2.h

0001 /*
0002  *  BSD LICENSE
0003  *
0004  *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
0005  *
0006  *  Redistribution and use in source and binary forms, with or without
0007  *  modification, are permitted provided that the following conditions
0008  *  are met:
0009  *
0010  *    * Redistributions of source code must retain the above copyright
0011  *      notice, this list of conditions and the following disclaimer.
0012  *    * Redistributions in binary form must reproduce the above copyright
0013  *      notice, this list of conditions and the following disclaimer in
0014  *      the documentation and/or other materials provided with the
0015  *      distribution.
0016  *    * Neither the name of Broadcom Corporation nor the names of its
0017  *      contributors may be used to endorse or promote products derived
0018  *      from this software without specific prior written permission.
0019  *
0020  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0021  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0022  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0023  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0024  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0025  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0026  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0027  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0028  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0029  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0030  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0031  */
0032
0033 #ifndef _CLOCK_BCM_NS2_H
0034 #define _CLOCK_BCM_NS2_H
0035
0036 /* GENPLL SCR clock channel ID */
0037 #define BCM_NS2_GENPLL_SCR      0
0038 #define BCM_NS2_GENPLL_SCR_SCR_CLK  1
0039 #define BCM_NS2_GENPLL_SCR_FS_CLK   2
0040 #define BCM_NS2_GENPLL_SCR_AUDIO_CLK    3
0041 #define BCM_NS2_GENPLL_SCR_CH3_UNUSED   4
0042 #define BCM_NS2_GENPLL_SCR_CH4_UNUSED   5
0043 #define BCM_NS2_GENPLL_SCR_CH5_UNUSED   6
0044
0045 /* GENPLL SW clock channel ID */
0046 #define BCM_NS2_GENPLL_SW       0
0047 #define BCM_NS2_GENPLL_SW_RPE_CLK   1
0048 #define BCM_NS2_GENPLL_SW_250_CLK   2
0049 #define BCM_NS2_GENPLL_SW_NIC_CLK   3
0050 #define BCM_NS2_GENPLL_SW_CHIMP_CLK 4
0051 #define BCM_NS2_GENPLL_SW_PORT_CLK  5
0052 #define BCM_NS2_GENPLL_SW_SDIO_CLK  6
0053
0054 /* LCPLL DDR clock channel ID */
0055 #define BCM_NS2_LCPLL_DDR       0
0056 #define BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK 1
0057 #define BCM_NS2_LCPLL_DDR_DDR_CLK   2
0058 #define BCM_NS2_LCPLL_DDR_CH2_UNUSED    3
0059 #define BCM_NS2_LCPLL_DDR_CH3_UNUSED    4
0060 #define BCM_NS2_LCPLL_DDR_CH4_UNUSED    5
0061 #define BCM_NS2_LCPLL_DDR_CH5_UNUSED    6
0062
0063 /* LCPLL PORTS clock channel ID */
0064 #define BCM_NS2_LCPLL_PORTS     0
0065 #define BCM_NS2_LCPLL_PORTS_WAN_CLK 1
0066 #define BCM_NS2_LCPLL_PORTS_RGMII_CLK   2
0067 #define BCM_NS2_LCPLL_PORTS_CH2_UNUSED  3
0068 #define BCM_NS2_LCPLL_PORTS_CH3_UNUSED  4
0069 #define BCM_NS2_LCPLL_PORTS_CH4_UNUSED  5
0070 #define BCM_NS2_LCPLL_PORTS_CH5_UNUSED  6
0071
0072 #endif /* _CLOCK_BCM_NS2_H */