dt-bindings/clock/axis%2Cartpec6-clkctrl.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * ARTPEC-6 clock controller indexes
0004  *
0005  * Copyright 2016 Axis Communications AB.
0006  */
0007
0008 #ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
0009 #define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
0010
0011 #define ARTPEC6_CLK_CPU         0
0012 #define ARTPEC6_CLK_CPU_PERIPH      1
0013 #define ARTPEC6_CLK_NAND_CLKA       2
0014 #define ARTPEC6_CLK_NAND_CLKB       3
0015 #define ARTPEC6_CLK_ETH_ACLK        4
0016 #define ARTPEC6_CLK_DMA_ACLK        5
0017 #define ARTPEC6_CLK_PTP_REF     6
0018 #define ARTPEC6_CLK_SD_PCLK     7
0019 #define ARTPEC6_CLK_SD_IMCLK        8
0020 #define ARTPEC6_CLK_I2S_HST     9
0021 #define ARTPEC6_CLK_I2S0_CLK        10
0022 #define ARTPEC6_CLK_I2S1_CLK        11
0023 #define ARTPEC6_CLK_UART_PCLK       12
0024 #define ARTPEC6_CLK_UART_REFCLK     13
0025 #define ARTPEC6_CLK_I2C         14
0026 #define ARTPEC6_CLK_SPI_PCLK        15
0027 #define ARTPEC6_CLK_SPI_SSPCLK      16
0028 #define ARTPEC6_CLK_SYS_TIMER       17
0029 #define ARTPEC6_CLK_FRACDIV_IN      18
0030 #define ARTPEC6_CLK_DBG_PCLK        19
0031
0032 /* This must be the highest clock index plus one. */
0033 #define ARTPEC6_CLK_NUMCLOCKS       20
0034
0035 #endif