dt-bindings/clock/am4.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright 2017 Texas Instruments, Inc.
0004  */
0005 #ifndef __DT_BINDINGS_CLK_AM4_H
0006 #define __DT_BINDINGS_CLK_AM4_H
0007
0008 #define AM4_CLKCTRL_OFFSET  0x20
0009 #define AM4_CLKCTRL_INDEX(offset)   ((offset) - AM4_CLKCTRL_OFFSET)
0010
0011 /* l3s_tsc clocks */
0012 #define AM4_L3S_TSC_CLKCTRL_OFFSET  0x120
0013 #define AM4_L3S_TSC_CLKCTRL_INDEX(offset)   ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET)
0014 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
0015
0016 /* l4_wkup_aon clocks */
0017 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET  0x228
0018 #define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset)   ((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET)
0019 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
0020 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
0021
0022 /* l4_wkup clocks */
0023 #define AM4_L4_WKUP_CLKCTRL_OFFSET  0x220
0024 #define AM4_L4_WKUP_CLKCTRL_INDEX(offset)   ((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET)
0025 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
0026 #define AM4_L4_WKUP_TIMER1_CLKCTRL  AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
0027 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL   AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
0028 #define AM4_L4_WKUP_I2C1_CLKCTRL    AM4_L4_WKUP_CLKCTRL_INDEX(0x340)
0029 #define AM4_L4_WKUP_UART1_CLKCTRL   AM4_L4_WKUP_CLKCTRL_INDEX(0x348)
0030 #define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL    AM4_L4_WKUP_CLKCTRL_INDEX(0x350)
0031 #define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL    AM4_L4_WKUP_CLKCTRL_INDEX(0x358)
0032 #define AM4_L4_WKUP_CONTROL_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x360)
0033 #define AM4_L4_WKUP_GPIO1_CLKCTRL   AM4_L4_WKUP_CLKCTRL_INDEX(0x368)
0034
0035 /* mpu clocks */
0036 #define AM4_MPU_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
0037
0038 /* gfx_l3 clocks */
0039 #define AM4_GFX_L3_GFX_CLKCTRL  AM4_CLKCTRL_INDEX(0x20)
0040
0041 /* l4_rtc clocks */
0042 #define AM4_L4_RTC_RTC_CLKCTRL  AM4_CLKCTRL_INDEX(0x20)
0043
0044 /* l3 clocks */
0045 #define AM4_L3_L3_MAIN_CLKCTRL  AM4_CLKCTRL_INDEX(0x20)
0046 #define AM4_L3_AES_CLKCTRL  AM4_CLKCTRL_INDEX(0x28)
0047 #define AM4_L3_DES_CLKCTRL  AM4_CLKCTRL_INDEX(0x30)
0048 #define AM4_L3_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40)
0049 #define AM4_L3_OCMCRAM_CLKCTRL  AM4_CLKCTRL_INDEX(0x50)
0050 #define AM4_L3_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58)
0051 #define AM4_L3_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78)
0052 #define AM4_L3_TPTC0_CLKCTRL    AM4_CLKCTRL_INDEX(0x80)
0053 #define AM4_L3_TPTC1_CLKCTRL    AM4_CLKCTRL_INDEX(0x88)
0054 #define AM4_L3_TPTC2_CLKCTRL    AM4_CLKCTRL_INDEX(0x90)
0055 #define AM4_L3_L4_HS_CLKCTRL    AM4_CLKCTRL_INDEX(0xa0)
0056
0057 /* l3s clocks */
0058 #define AM4_L3S_CLKCTRL_OFFSET  0x68
0059 #define AM4_L3S_CLKCTRL_INDEX(offset)   ((offset) - AM4_L3S_CLKCTRL_OFFSET)
0060 #define AM4_L3S_VPFE0_CLKCTRL   AM4_L3S_CLKCTRL_INDEX(0x68)
0061 #define AM4_L3S_VPFE1_CLKCTRL   AM4_L3S_CLKCTRL_INDEX(0x70)
0062 #define AM4_L3S_GPMC_CLKCTRL    AM4_L3S_CLKCTRL_INDEX(0x220)
0063 #define AM4_L3S_ADC1_CLKCTRL    AM4_L3S_CLKCTRL_INDEX(0x230)
0064 #define AM4_L3S_MCASP0_CLKCTRL  AM4_L3S_CLKCTRL_INDEX(0x238)
0065 #define AM4_L3S_MCASP1_CLKCTRL  AM4_L3S_CLKCTRL_INDEX(0x240)
0066 #define AM4_L3S_MMC3_CLKCTRL    AM4_L3S_CLKCTRL_INDEX(0x248)
0067 #define AM4_L3S_QSPI_CLKCTRL    AM4_L3S_CLKCTRL_INDEX(0x258)
0068 #define AM4_L3S_USB_OTG_SS0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x260)
0069 #define AM4_L3S_USB_OTG_SS1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x268)
0070
0071 /* pruss_ocp clocks */
0072 #define AM4_PRUSS_OCP_CLKCTRL_OFFSET    0x320
0073 #define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET)
0074 #define AM4_PRUSS_OCP_PRUSS_CLKCTRL AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320)
0075
0076 /* l4ls clocks */
0077 #define AM4_L4LS_CLKCTRL_OFFSET 0x420
0078 #define AM4_L4LS_CLKCTRL_INDEX(offset)  ((offset) - AM4_L4LS_CLKCTRL_OFFSET)
0079 #define AM4_L4LS_L4_LS_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x420)
0080 #define AM4_L4LS_D_CAN0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x428)
0081 #define AM4_L4LS_D_CAN1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x430)
0082 #define AM4_L4LS_EPWMSS0_CLKCTRL    AM4_L4LS_CLKCTRL_INDEX(0x438)
0083 #define AM4_L4LS_EPWMSS1_CLKCTRL    AM4_L4LS_CLKCTRL_INDEX(0x440)
0084 #define AM4_L4LS_EPWMSS2_CLKCTRL    AM4_L4LS_CLKCTRL_INDEX(0x448)
0085 #define AM4_L4LS_EPWMSS3_CLKCTRL    AM4_L4LS_CLKCTRL_INDEX(0x450)
0086 #define AM4_L4LS_EPWMSS4_CLKCTRL    AM4_L4LS_CLKCTRL_INDEX(0x458)
0087 #define AM4_L4LS_EPWMSS5_CLKCTRL    AM4_L4LS_CLKCTRL_INDEX(0x460)
0088 #define AM4_L4LS_ELM_CLKCTRL    AM4_L4LS_CLKCTRL_INDEX(0x468)
0089 #define AM4_L4LS_GPIO2_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x478)
0090 #define AM4_L4LS_GPIO3_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x480)
0091 #define AM4_L4LS_GPIO4_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x488)
0092 #define AM4_L4LS_GPIO5_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x490)
0093 #define AM4_L4LS_GPIO6_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x498)
0094 #define AM4_L4LS_HDQ1W_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x4a0)
0095 #define AM4_L4LS_I2C2_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x4a8)
0096 #define AM4_L4LS_I2C3_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x4b0)
0097 #define AM4_L4LS_MAILBOX_CLKCTRL    AM4_L4LS_CLKCTRL_INDEX(0x4b8)
0098 #define AM4_L4LS_MMC1_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x4c0)
0099 #define AM4_L4LS_MMC2_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x4c8)
0100 #define AM4_L4LS_RNG_CLKCTRL    AM4_L4LS_CLKCTRL_INDEX(0x4e0)
0101 #define AM4_L4LS_SPI0_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x500)
0102 #define AM4_L4LS_SPI1_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x508)
0103 #define AM4_L4LS_SPI2_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x510)
0104 #define AM4_L4LS_SPI3_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x518)
0105 #define AM4_L4LS_SPI4_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x520)
0106 #define AM4_L4LS_SPINLOCK_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x528)
0107 #define AM4_L4LS_TIMER2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x530)
0108 #define AM4_L4LS_TIMER3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x538)
0109 #define AM4_L4LS_TIMER4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x540)
0110 #define AM4_L4LS_TIMER5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x548)
0111 #define AM4_L4LS_TIMER6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x550)
0112 #define AM4_L4LS_TIMER7_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x558)
0113 #define AM4_L4LS_TIMER8_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x560)
0114 #define AM4_L4LS_TIMER9_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x568)
0115 #define AM4_L4LS_TIMER10_CLKCTRL    AM4_L4LS_CLKCTRL_INDEX(0x570)
0116 #define AM4_L4LS_TIMER11_CLKCTRL    AM4_L4LS_CLKCTRL_INDEX(0x578)
0117 #define AM4_L4LS_UART2_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x580)
0118 #define AM4_L4LS_UART3_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x588)
0119 #define AM4_L4LS_UART4_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x590)
0120 #define AM4_L4LS_UART5_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x598)
0121 #define AM4_L4LS_UART6_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x5a0)
0122 #define AM4_L4LS_OCP2SCP0_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x5b8)
0123 #define AM4_L4LS_OCP2SCP1_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x5c0)
0124
0125 /* emif clocks */
0126 #define AM4_EMIF_CLKCTRL_OFFSET 0x720
0127 #define AM4_EMIF_CLKCTRL_INDEX(offset)  ((offset) - AM4_EMIF_CLKCTRL_OFFSET)
0128 #define AM4_EMIF_EMIF_CLKCTRL   AM4_EMIF_CLKCTRL_INDEX(0x720)
0129
0130 /* dss clocks */
0131 #define AM4_DSS_CLKCTRL_OFFSET  0xa20
0132 #define AM4_DSS_CLKCTRL_INDEX(offset)   ((offset) - AM4_DSS_CLKCTRL_OFFSET)
0133 #define AM4_DSS_DSS_CORE_CLKCTRL    AM4_DSS_CLKCTRL_INDEX(0xa20)
0134
0135 /* cpsw_125mhz clocks */
0136 #define AM4_CPSW_125MHZ_CLKCTRL_OFFSET  0xb20
0137 #define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset)   ((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET)
0138 #define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20)
0139
0140 #endif