dt-bindings/clock/am3.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright 2017 Texas Instruments, Inc.
0004  */
0005 #ifndef __DT_BINDINGS_CLK_AM3_H
0006 #define __DT_BINDINGS_CLK_AM3_H
0007
0008 #define AM3_CLKCTRL_OFFSET  0x0
0009 #define AM3_CLKCTRL_INDEX(offset)   ((offset) - AM3_CLKCTRL_OFFSET)
0010
0011 /* l4ls clocks */
0012 #define AM3_L4LS_CLKCTRL_OFFSET 0x38
0013 #define AM3_L4LS_CLKCTRL_INDEX(offset)  ((offset) - AM3_L4LS_CLKCTRL_OFFSET)
0014 #define AM3_L4LS_UART6_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x38)
0015 #define AM3_L4LS_MMC1_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x3c)
0016 #define AM3_L4LS_ELM_CLKCTRL    AM3_L4LS_CLKCTRL_INDEX(0x40)
0017 #define AM3_L4LS_I2C3_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x44)
0018 #define AM3_L4LS_I2C2_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x48)
0019 #define AM3_L4LS_SPI0_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x4c)
0020 #define AM3_L4LS_SPI1_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x50)
0021 #define AM3_L4LS_L4_LS_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x60)
0022 #define AM3_L4LS_UART2_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x6c)
0023 #define AM3_L4LS_UART3_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x70)
0024 #define AM3_L4LS_UART4_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x74)
0025 #define AM3_L4LS_UART5_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x78)
0026 #define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c)
0027 #define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80)
0028 #define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84)
0029 #define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88)
0030 #define AM3_L4LS_RNG_CLKCTRL    AM3_L4LS_CLKCTRL_INDEX(0x90)
0031 #define AM3_L4LS_GPIO2_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0xac)
0032 #define AM3_L4LS_GPIO3_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0xb0)
0033 #define AM3_L4LS_GPIO4_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0xb4)
0034 #define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0)
0035 #define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4)
0036 #define AM3_L4LS_EPWMSS1_CLKCTRL    AM3_L4LS_CLKCTRL_INDEX(0xcc)
0037 #define AM3_L4LS_EPWMSS0_CLKCTRL    AM3_L4LS_CLKCTRL_INDEX(0xd4)
0038 #define AM3_L4LS_EPWMSS2_CLKCTRL    AM3_L4LS_CLKCTRL_INDEX(0xd8)
0039 #define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec)
0040 #define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0)
0041 #define AM3_L4LS_MMC2_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0xf4)
0042 #define AM3_L4LS_SPINLOCK_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x10c)
0043 #define AM3_L4LS_MAILBOX_CLKCTRL    AM3_L4LS_CLKCTRL_INDEX(0x110)
0044 #define AM3_L4LS_OCPWP_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x130)
0045
0046 /* l3s clocks */
0047 #define AM3_L3S_CLKCTRL_OFFSET  0x1c
0048 #define AM3_L3S_CLKCTRL_INDEX(offset)   ((offset) - AM3_L3S_CLKCTRL_OFFSET)
0049 #define AM3_L3S_USB_OTG_HS_CLKCTRL  AM3_L3S_CLKCTRL_INDEX(0x1c)
0050 #define AM3_L3S_GPMC_CLKCTRL    AM3_L3S_CLKCTRL_INDEX(0x30)
0051 #define AM3_L3S_MCASP0_CLKCTRL  AM3_L3S_CLKCTRL_INDEX(0x34)
0052 #define AM3_L3S_MCASP1_CLKCTRL  AM3_L3S_CLKCTRL_INDEX(0x68)
0053 #define AM3_L3S_MMC3_CLKCTRL    AM3_L3S_CLKCTRL_INDEX(0xf8)
0054
0055 /* l3 clocks */
0056 #define AM3_L3_CLKCTRL_OFFSET   0x24
0057 #define AM3_L3_CLKCTRL_INDEX(offset)    ((offset) - AM3_L3_CLKCTRL_OFFSET)
0058 #define AM3_L3_TPTC0_CLKCTRL    AM3_L3_CLKCTRL_INDEX(0x24)
0059 #define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28)
0060 #define AM3_L3_OCMCRAM_CLKCTRL  AM3_L3_CLKCTRL_INDEX(0x2c)
0061 #define AM3_L3_AES_CLKCTRL  AM3_L3_CLKCTRL_INDEX(0x94)
0062 #define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0)
0063 #define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc)
0064 #define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc)
0065 #define AM3_L3_L3_MAIN_CLKCTRL  AM3_L3_CLKCTRL_INDEX(0xe0)
0066 #define AM3_L3_TPTC1_CLKCTRL    AM3_L3_CLKCTRL_INDEX(0xfc)
0067 #define AM3_L3_TPTC2_CLKCTRL    AM3_L3_CLKCTRL_INDEX(0x100)
0068
0069 /* l4hs clocks */
0070 #define AM3_L4HS_CLKCTRL_OFFSET 0x120
0071 #define AM3_L4HS_CLKCTRL_INDEX(offset)  ((offset) - AM3_L4HS_CLKCTRL_OFFSET)
0072 #define AM3_L4HS_L4_HS_CLKCTRL  AM3_L4HS_CLKCTRL_INDEX(0x120)
0073
0074 /* pruss_ocp clocks */
0075 #define AM3_PRUSS_OCP_CLKCTRL_OFFSET    0xe8
0076 #define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET)
0077 #define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8)
0078
0079 /* cpsw_125mhz clocks */
0080 #define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14)
0081
0082 /* lcdc clocks */
0083 #define AM3_LCDC_CLKCTRL_OFFSET 0x18
0084 #define AM3_LCDC_CLKCTRL_INDEX(offset)  ((offset) - AM3_LCDC_CLKCTRL_OFFSET)
0085 #define AM3_LCDC_LCDC_CLKCTRL   AM3_LCDC_CLKCTRL_INDEX(0x18)
0086
0087 /* clk_24mhz clocks */
0088 #define AM3_CLK_24MHZ_CLKCTRL_OFFSET    0x14c
0089 #define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET)
0090 #define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c)
0091
0092 /* l4_wkup clocks */
0093 #define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
0094 #define AM3_L4_WKUP_GPIO1_CLKCTRL   AM3_CLKCTRL_INDEX(0x8)
0095 #define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc)
0096 #define AM3_L4_WKUP_UART1_CLKCTRL   AM3_CLKCTRL_INDEX(0xb4)
0097 #define AM3_L4_WKUP_I2C1_CLKCTRL    AM3_CLKCTRL_INDEX(0xb8)
0098 #define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc)
0099 #define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL    AM3_CLKCTRL_INDEX(0xc0)
0100 #define AM3_L4_WKUP_TIMER1_CLKCTRL  AM3_CLKCTRL_INDEX(0xc4)
0101 #define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL    AM3_CLKCTRL_INDEX(0xc8)
0102 #define AM3_L4_WKUP_WD_TIMER2_CLKCTRL   AM3_CLKCTRL_INDEX(0xd4)
0103
0104 /* l3_aon clocks */
0105 #define AM3_L3_AON_CLKCTRL_OFFSET   0x14
0106 #define AM3_L3_AON_CLKCTRL_INDEX(offset)    ((offset) - AM3_L3_AON_CLKCTRL_OFFSET)
0107 #define AM3_L3_AON_DEBUGSS_CLKCTRL  AM3_L3_AON_CLKCTRL_INDEX(0x14)
0108
0109 /* l4_wkup_aon clocks */
0110 #define AM3_L4_WKUP_AON_CLKCTRL_OFFSET  0xb0
0111 #define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset)   ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET)
0112 #define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0)
0113
0114 /* mpu clocks */
0115 #define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
0116
0117 /* l4_rtc clocks */
0118 #define AM3_L4_RTC_RTC_CLKCTRL  AM3_CLKCTRL_INDEX(0x0)
0119
0120 /* gfx_l3 clocks */
0121 #define AM3_GFX_L3_GFX_CLKCTRL  AM3_CLKCTRL_INDEX(0x4)
0122
0123 /* l4_cefuse clocks */
0124 #define AM3_L4_CEFUSE_CEFUSE_CLKCTRL    AM3_CLKCTRL_INDEX(0x20)
0125
0126 #endif