dt-bindings/clock/agilex-clock.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2019, Intel Corporation
0004  */
0005
0006 #ifndef __AGILEX_CLOCK_H
0007 #define __AGILEX_CLOCK_H
0008
0009 /* fixed rate clocks */
0010 #define AGILEX_OSC1         0
0011 #define AGILEX_CB_INTOSC_HS_DIV2_CLK    1
0012 #define AGILEX_CB_INTOSC_LS_CLK     2
0013 #define AGILEX_L4_SYS_FREE_CLK      3
0014 #define AGILEX_F2S_FREE_CLK     4
0015
0016 /* PLL clocks */
0017 #define AGILEX_MAIN_PLL_CLK     5
0018 #define AGILEX_MAIN_PLL_C0_CLK      6
0019 #define AGILEX_MAIN_PLL_C1_CLK      7
0020 #define AGILEX_MAIN_PLL_C2_CLK      8
0021 #define AGILEX_MAIN_PLL_C3_CLK      9
0022 #define AGILEX_PERIPH_PLL_CLK       10
0023 #define AGILEX_PERIPH_PLL_C0_CLK    11
0024 #define AGILEX_PERIPH_PLL_C1_CLK    12
0025 #define AGILEX_PERIPH_PLL_C2_CLK    13
0026 #define AGILEX_PERIPH_PLL_C3_CLK    14
0027 #define AGILEX_MPU_FREE_CLK     15
0028 #define AGILEX_MPU_CCU_CLK      16
0029 #define AGILEX_BOOT_CLK         17
0030
0031 /* fixed factor clocks */
0032 #define AGILEX_L3_MAIN_FREE_CLK     18
0033 #define AGILEX_NOC_FREE_CLK     19
0034 #define AGILEX_S2F_USR0_CLK     20
0035 #define AGILEX_NOC_CLK          21
0036 #define AGILEX_EMAC_A_FREE_CLK      22
0037 #define AGILEX_EMAC_B_FREE_CLK      23
0038 #define AGILEX_EMAC_PTP_FREE_CLK    24
0039 #define AGILEX_GPIO_DB_FREE_CLK     25
0040 #define AGILEX_SDMMC_FREE_CLK       26
0041 #define AGILEX_S2F_USER0_FREE_CLK   27
0042 #define AGILEX_S2F_USER1_FREE_CLK   28
0043 #define AGILEX_PSI_REF_FREE_CLK     29
0044
0045 /* Gate clocks */
0046 #define AGILEX_MPU_CLK          30
0047 #define AGILEX_MPU_L2RAM_CLK        31
0048 #define AGILEX_MPU_PERIPH_CLK       32
0049 #define AGILEX_L4_MAIN_CLK      33
0050 #define AGILEX_L4_MP_CLK        34
0051 #define AGILEX_L4_SP_CLK        35
0052 #define AGILEX_CS_AT_CLK        36
0053 #define AGILEX_CS_TRACE_CLK     37
0054 #define AGILEX_CS_PDBG_CLK      38
0055 #define AGILEX_CS_TIMER_CLK     39
0056 #define AGILEX_S2F_USER0_CLK        40
0057 #define AGILEX_EMAC0_CLK        41
0058 #define AGILEX_EMAC1_CLK        43
0059 #define AGILEX_EMAC2_CLK        44
0060 #define AGILEX_EMAC_PTP_CLK     45
0061 #define AGILEX_GPIO_DB_CLK      46
0062 #define AGILEX_NAND_CLK         47
0063 #define AGILEX_PSI_REF_CLK      48
0064 #define AGILEX_S2F_USER1_CLK        49
0065 #define AGILEX_SDMMC_CLK        50
0066 #define AGILEX_SPI_M_CLK        51
0067 #define AGILEX_USB_CLK          52
0068 #define AGILEX_NAND_X_CLK       53
0069 #define AGILEX_NAND_ECC_CLK     54
0070 #define AGILEX_NUM_CLKS         55
0071
0072 #endif  /* __AGILEX_CLOCK_H */