dt-bindings/clock/actions%2Cs700-cmu.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Device Tree binding constants for Actions Semi S700 Clock Management Unit
0004  *
0005  * Copyright (c) 2014 Actions Semi Inc.
0006  * Author: David Liu <liuwei@actions-semi.com>
0007  *
0008  * Author: Pathiban Nallathambi <pn@denx.de>
0009  * Author: Saravanan Sekar <sravanhome@gmail.com>
0010  */
0011
0012 #ifndef __DT_BINDINGS_CLOCK_S700_H
0013 #define __DT_BINDINGS_CLOCK_S700_H
0014
0015 #define CLK_NONE            0
0016
0017 /* pll clocks */
0018 #define CLK_CORE_PLL            1
0019 #define CLK_DEV_PLL         2
0020 #define CLK_DDR_PLL         3
0021 #define CLK_NAND_PLL            4
0022 #define CLK_DISPLAY_PLL         5
0023 #define CLK_TVOUT_PLL           6
0024 #define CLK_CVBS_PLL            7
0025 #define CLK_AUDIO_PLL           8
0026 #define CLK_ETHERNET_PLL        9
0027
0028 /* system clock */
0029 #define CLK_CPU             10
0030 #define CLK_DEV             11
0031 #define CLK_AHB             12
0032 #define CLK_APB             13
0033 #define CLK_DMAC            14
0034 #define CLK_NOC0_CLK_MUX        15
0035 #define CLK_NOC1_CLK_MUX        16
0036 #define CLK_HP_CLK_MUX          17
0037 #define CLK_HP_CLK_DIV          18
0038 #define CLK_NOC1_CLK_DIV        19
0039 #define CLK_NOC0            20
0040 #define CLK_NOC1            21
0041 #define CLK_SENOR_SRC           22
0042
0043 /* peripheral device clock */
0044 #define CLK_GPIO            23
0045 #define CLK_TIMER           24
0046 #define CLK_DSI             25
0047 #define CLK_CSI             26
0048 #define CLK_SI              27
0049 #define CLK_DE              28
0050 #define CLK_HDE             29
0051 #define CLK_VDE             30
0052 #define CLK_VCE             31
0053 #define CLK_NAND            32
0054 #define CLK_SD0             33
0055 #define CLK_SD1             34
0056 #define CLK_SD2             35
0057
0058 #define CLK_UART0           36
0059 #define CLK_UART1           37
0060 #define CLK_UART2           38
0061 #define CLK_UART3           39
0062 #define CLK_UART4           40
0063 #define CLK_UART5           41
0064 #define CLK_UART6           42
0065
0066 #define CLK_PWM0            43
0067 #define CLK_PWM1            44
0068 #define CLK_PWM2            45
0069 #define CLK_PWM3            46
0070 #define CLK_PWM4            47
0071 #define CLK_PWM5            48
0072 #define CLK_GPU3D           49
0073
0074 #define CLK_I2C0            50
0075 #define CLK_I2C1            51
0076 #define CLK_I2C2            52
0077 #define CLK_I2C3            53
0078
0079 #define CLK_SPI0            54
0080 #define CLK_SPI1            55
0081 #define CLK_SPI2            56
0082 #define CLK_SPI3            57
0083
0084 #define CLK_USB3_480MPLL0       58
0085 #define CLK_USB3_480MPHY0       59
0086 #define CLK_USB3_5GPHY          60
0087 #define CLK_USB3_CCE            61
0088 #define CLK_USB3_MAC            62
0089
0090 #define CLK_LCD             63
0091 #define CLK_HDMI_AUDIO          64
0092 #define CLK_I2SRX           65
0093 #define CLK_I2STX           66
0094
0095 #define CLK_SENSOR0         67
0096 #define CLK_SENSOR1         68
0097
0098 #define CLK_HDMI_DEV            69
0099
0100 #define CLK_ETHERNET            70
0101 #define CLK_RMII_REF            71
0102
0103 #define CLK_USB2H0_PLLEN        72
0104 #define CLK_USB2H0_PHY          73
0105 #define CLK_USB2H0_CCE          74
0106 #define CLK_USB2H1_PLLEN        75
0107 #define CLK_USB2H1_PHY          76
0108 #define CLK_USB2H1_CCE          77
0109
0110 #define CLK_TVOUT           78
0111
0112 #define CLK_THERMAL_SENSOR      79
0113
0114 #define CLK_IRC_SWITCH          80
0115 #define CLK_PCM1            81
0116 #define CLK_NR_CLKS         (CLK_PCM1 + 1)
0117
0118 #endif /* __DT_BINDINGS_CLOCK_S700_H */