dt-bindings/clock/actions%2Cs500-cmu.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Device Tree binding constants for Actions Semi S500 Clock Management Unit
0004  *
0005  * Copyright (c) 2014 Actions Semi Inc.
0006  * Copyright (c) 2018 LSI-TEC - Caninos Loucos
0007  */
0008
0009 #ifndef __DT_BINDINGS_CLOCK_S500_CMU_H
0010 #define __DT_BINDINGS_CLOCK_S500_CMU_H
0011
0012 #define CLK_NONE        0
0013
0014 /* fixed rate clocks */
0015 #define CLK_LOSC        1
0016 #define CLK_HOSC        2
0017
0018 /* pll clocks */
0019 #define CLK_CORE_PLL        3
0020 #define CLK_DEV_PLL     4
0021 #define CLK_DDR_PLL     5
0022 #define CLK_NAND_PLL        6
0023 #define CLK_DISPLAY_PLL     7
0024 #define CLK_ETHERNET_PLL    8
0025 #define CLK_AUDIO_PLL       9
0026
0027 /* system clock */
0028 #define CLK_DEV         10
0029 #define CLK_H           11
0030 #define CLK_AHBPREDIV       12
0031 #define CLK_AHB         13
0032 #define CLK_DE          14
0033 #define CLK_BISP        15
0034 #define CLK_VCE         16
0035 #define CLK_VDE         17
0036
0037 /* peripheral device clock */
0038 #define CLK_TIMER       18
0039 #define CLK_I2C0        19
0040 #define CLK_I2C1        20
0041 #define CLK_I2C2        21
0042 #define CLK_I2C3        22
0043 #define CLK_PWM0        23
0044 #define CLK_PWM1        24
0045 #define CLK_PWM2        25
0046 #define CLK_PWM3        26
0047 #define CLK_PWM4        27
0048 #define CLK_PWM5        28
0049 #define CLK_SD0         29
0050 #define CLK_SD1         30
0051 #define CLK_SD2         31
0052 #define CLK_SENSOR0     32
0053 #define CLK_SENSOR1     33
0054 #define CLK_SPI0        34
0055 #define CLK_SPI1        35
0056 #define CLK_SPI2        36
0057 #define CLK_SPI3        37
0058 #define CLK_UART0       38
0059 #define CLK_UART1       39
0060 #define CLK_UART2       40
0061 #define CLK_UART3       41
0062 #define CLK_UART4       42
0063 #define CLK_UART5       43
0064 #define CLK_UART6       44
0065 #define CLK_DE1         45
0066 #define CLK_DE2         46
0067 #define CLK_I2SRX       47
0068 #define CLK_I2STX       48
0069 #define CLK_HDMI_AUDIO      49
0070 #define CLK_HDMI        50
0071 #define CLK_SPDIF       51
0072 #define CLK_NAND        52
0073 #define CLK_ECC         53
0074 #define CLK_RMII_REF        54
0075 #define CLK_GPIO        55
0076
0077 /* additional clocks */
0078 #define CLK_APB         56
0079 #define CLK_DMAC        57
0080 #define CLK_NIC         58
0081 #define CLK_ETHERNET        59
0082
0083 #define CLK_NR_CLKS     (CLK_ETHERNET + 1)
0084
0085 #endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */