include/drm/i915_drm.h

0001 /*
0002  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
0003  * All Rights Reserved.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the
0007  * "Software"), to deal in the Software without restriction, including
0008  * without limitation the rights to use, copy, modify, merge, publish,
0009  * distribute, sub license, and/or sell copies of the Software, and to
0010  * permit persons to whom the Software is furnished to do so, subject to
0011  * the following conditions:
0012  *
0013  * The above copyright notice and this permission notice (including the
0014  * next paragraph) shall be included in all copies or substantial portions
0015  * of the Software.
0016  *
0017  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
0018  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0019  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
0020  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
0021  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
0022  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
0023  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0024  *
0025  */
0026 #ifndef _I915_DRM_H_
0027 #define _I915_DRM_H_
0028
0029 #include <linux/types.h>
0030
0031 /* For use by IPS driver */
0032 unsigned long i915_read_mch_val(void);
0033 bool i915_gpu_raise(void);
0034 bool i915_gpu_lower(void);
0035 bool i915_gpu_busy(void);
0036 bool i915_gpu_turbo_disable(void);
0037
0038 /* Exported from arch/x86/kernel/early-quirks.c */
0039 extern struct resource intel_graphics_stolen_res;
0040
0041 /*
0042  * The Bridge device's PCI config space has information about the
0043  * fb aperture size and the amount of pre-reserved memory.
0044  * This is all handled in the intel-gtt.ko module. i915.ko only
0045  * cares about the vga bit for the vga rbiter.
0046  */
0047 #define INTEL_GMCH_CTRL     0x52
0048 #define INTEL_GMCH_VGA_DISABLE  (1 << 1)
0049 #define SNB_GMCH_CTRL       0x50
0050 #define    SNB_GMCH_GGMS_SHIFT  8 /* GTT Graphics Memory Size */
0051 #define    SNB_GMCH_GGMS_MASK   0x3
0052 #define    SNB_GMCH_GMS_SHIFT   3 /* Graphics Mode Select */
0053 #define    SNB_GMCH_GMS_MASK    0x1f
0054 #define    BDW_GMCH_GGMS_SHIFT  6
0055 #define    BDW_GMCH_GGMS_MASK   0x3
0056 #define    BDW_GMCH_GMS_SHIFT   8
0057 #define    BDW_GMCH_GMS_MASK    0xff
0058
0059 #define I830_GMCH_CTRL          0x52
0060
0061 #define I830_GMCH_GMS_MASK      0x70
0062 #define I830_GMCH_GMS_LOCAL     0x10
0063 #define I830_GMCH_GMS_STOLEN_512    0x20
0064 #define I830_GMCH_GMS_STOLEN_1024   0x30
0065 #define I830_GMCH_GMS_STOLEN_8192   0x40
0066
0067 #define I855_GMCH_GMS_MASK      0xF0
0068 #define I855_GMCH_GMS_STOLEN_0M     0x0
0069 #define I855_GMCH_GMS_STOLEN_1M     (0x1 << 4)
0070 #define I855_GMCH_GMS_STOLEN_4M     (0x2 << 4)
0071 #define I855_GMCH_GMS_STOLEN_8M     (0x3 << 4)
0072 #define I855_GMCH_GMS_STOLEN_16M    (0x4 << 4)
0073 #define I855_GMCH_GMS_STOLEN_32M    (0x5 << 4)
0074 #define I915_GMCH_GMS_STOLEN_48M    (0x6 << 4)
0075 #define I915_GMCH_GMS_STOLEN_64M    (0x7 << 4)
0076 #define G33_GMCH_GMS_STOLEN_128M    (0x8 << 4)
0077 #define G33_GMCH_GMS_STOLEN_256M    (0x9 << 4)
0078 #define INTEL_GMCH_GMS_STOLEN_96M   (0xa << 4)
0079 #define INTEL_GMCH_GMS_STOLEN_160M  (0xb << 4)
0080 #define INTEL_GMCH_GMS_STOLEN_224M  (0xc << 4)
0081 #define INTEL_GMCH_GMS_STOLEN_352M  (0xd << 4)
0082
0083 #define I830_DRB3       0x63
0084 #define I85X_DRB3       0x43
0085 #define I865_TOUD       0xc4
0086
0087 #define I830_ESMRAMC        0x91
0088 #define I845_ESMRAMC        0x9e
0089 #define I85X_ESMRAMC        0x61
0090 #define    TSEG_ENABLE      (1 << 0)
0091 #define    I830_TSEG_SIZE_512K  (0 << 1)
0092 #define    I830_TSEG_SIZE_1M    (1 << 1)
0093 #define    I845_TSEG_SIZE_MASK  (3 << 1)
0094 #define    I845_TSEG_SIZE_512K  (2 << 1)
0095 #define    I845_TSEG_SIZE_1M    (3 << 1)
0096
0097 #define INTEL_BSM       0x5c
0098 #define INTEL_GEN11_BSM_DW0 0xc0
0099 #define INTEL_GEN11_BSM_DW1 0xc4
0100 #define   INTEL_BSM_MASK    (-(1u << 20))
0101
0102 #endif              /* _I915_DRM_H_ */