include/drm/drm_edid.h

0001 /*
0002  * Copyright © 2007-2008 Intel Corporation
0003  *   Jesse Barnes <jesse.barnes@intel.com>
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  */
0023 #ifndef __DRM_EDID_H__
0024 #define __DRM_EDID_H__
0025
0026 #include <linux/types.h>
0027 #include <linux/hdmi.h>
0028 #include <drm/drm_mode.h>
0029
0030 struct drm_device;
0031 struct drm_edid;
0032 struct i2c_adapter;
0033
0034 #define EDID_LENGTH 128
0035 #define DDC_ADDR 0x50
0036 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */
0037
0038 #define CEA_EXT     0x02
0039 #define VTB_EXT     0x10
0040 #define DI_EXT      0x40
0041 #define LS_EXT      0x50
0042 #define MI_EXT      0x60
0043 #define DISPLAYID_EXT 0x70
0044
0045 struct est_timings {
0046     u8 t1;
0047     u8 t2;
0048     u8 mfg_rsvd;
0049 } __attribute__((packed));
0050
0051 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
0052 #define EDID_TIMING_ASPECT_SHIFT 6
0053 #define EDID_TIMING_ASPECT_MASK  (0x3 << EDID_TIMING_ASPECT_SHIFT)
0054
0055 /* need to add 60 */
0056 #define EDID_TIMING_VFREQ_SHIFT  0
0057 #define EDID_TIMING_VFREQ_MASK   (0x3f << EDID_TIMING_VFREQ_SHIFT)
0058
0059 struct std_timing {
0060     u8 hsize; /* need to multiply by 8 then add 248 */
0061     u8 vfreq_aspect;
0062 } __attribute__((packed));
0063
0064 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
0065 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
0066 #define DRM_EDID_PT_SEPARATE_SYNC  (3 << 3)
0067 #define DRM_EDID_PT_STEREO         (1 << 5)
0068 #define DRM_EDID_PT_INTERLACED     (1 << 7)
0069
0070 /* If detailed data is pixel timing */
0071 struct detailed_pixel_timing {
0072     u8 hactive_lo;
0073     u8 hblank_lo;
0074     u8 hactive_hblank_hi;
0075     u8 vactive_lo;
0076     u8 vblank_lo;
0077     u8 vactive_vblank_hi;
0078     u8 hsync_offset_lo;
0079     u8 hsync_pulse_width_lo;
0080     u8 vsync_offset_pulse_width_lo;
0081     u8 hsync_vsync_offset_pulse_width_hi;
0082     u8 width_mm_lo;
0083     u8 height_mm_lo;
0084     u8 width_height_mm_hi;
0085     u8 hborder;
0086     u8 vborder;
0087     u8 misc;
0088 } __attribute__((packed));
0089
0090 /* If it's not pixel timing, it'll be one of the below */
0091 struct detailed_data_string {
0092     u8 str[13];
0093 } __attribute__((packed));
0094
0095 #define DRM_EDID_RANGE_OFFSET_MIN_VFREQ (1 << 0) /* 1.4 */
0096 #define DRM_EDID_RANGE_OFFSET_MAX_VFREQ (1 << 1) /* 1.4 */
0097 #define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 << 2) /* 1.4 */
0098 #define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.4 */
0099
0100 #define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG   0x00
0101 #define DRM_EDID_RANGE_LIMITS_ONLY_FLAG     0x01
0102 #define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02
0103 #define DRM_EDID_CVT_SUPPORT_FLAG           0x04
0104
0105 struct detailed_data_monitor_range {
0106     u8 min_vfreq;
0107     u8 max_vfreq;
0108     u8 min_hfreq_khz;
0109     u8 max_hfreq_khz;
0110     u8 pixel_clock_mhz; /* need to multiply by 10 */
0111     u8 flags;
0112     union {
0113         struct {
0114             u8 reserved;
0115             u8 hfreq_start_khz; /* need to multiply by 2 */
0116             u8 c; /* need to divide by 2 */
0117             __le16 m;
0118             u8 k;
0119             u8 j; /* need to divide by 2 */
0120         } __attribute__((packed)) gtf2;
0121         struct {
0122             u8 version;
0123             u8 data1; /* high 6 bits: extra clock resolution */
0124             u8 data2; /* plus low 2 of above: max hactive */
0125             u8 supported_aspects;
0126             u8 flags; /* preferred aspect and blanking support */
0127             u8 supported_scalings;
0128             u8 preferred_refresh;
0129         } __attribute__((packed)) cvt;
0130     } __attribute__((packed)) formula;
0131 } __attribute__((packed));
0132
0133 struct detailed_data_wpindex {
0134     u8 white_yx_lo; /* Lower 2 bits each */
0135     u8 white_x_hi;
0136     u8 white_y_hi;
0137     u8 gamma; /* need to divide by 100 then add 1 */
0138 } __attribute__((packed));
0139
0140 struct detailed_data_color_point {
0141     u8 windex1;
0142     u8 wpindex1[3];
0143     u8 windex2;
0144     u8 wpindex2[3];
0145 } __attribute__((packed));
0146
0147 struct cvt_timing {
0148     u8 code[3];
0149 } __attribute__((packed));
0150
0151 struct detailed_non_pixel {
0152     u8 pad1;
0153     u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
0154             fb=color point data, fa=standard timing data,
0155             f9=undefined, f8=mfg. reserved */
0156     u8 pad2;
0157     union {
0158         struct detailed_data_string str;
0159         struct detailed_data_monitor_range range;
0160         struct detailed_data_wpindex color;
0161         struct std_timing timings[6];
0162         struct cvt_timing cvt[4];
0163     } __attribute__((packed)) data;
0164 } __attribute__((packed));
0165
0166 #define EDID_DETAIL_EST_TIMINGS 0xf7
0167 #define EDID_DETAIL_CVT_3BYTE 0xf8
0168 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
0169 #define EDID_DETAIL_STD_MODES 0xfa
0170 #define EDID_DETAIL_MONITOR_CPDATA 0xfb
0171 #define EDID_DETAIL_MONITOR_NAME 0xfc
0172 #define EDID_DETAIL_MONITOR_RANGE 0xfd
0173 #define EDID_DETAIL_MONITOR_STRING 0xfe
0174 #define EDID_DETAIL_MONITOR_SERIAL 0xff
0175
0176 struct detailed_timing {
0177     __le16 pixel_clock; /* need to multiply by 10 KHz */
0178     union {
0179         struct detailed_pixel_timing pixel_data;
0180         struct detailed_non_pixel other_data;
0181     } __attribute__((packed)) data;
0182 } __attribute__((packed));
0183
0184 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
0185 #define DRM_EDID_INPUT_SYNC_ON_GREEN   (1 << 1)
0186 #define DRM_EDID_INPUT_COMPOSITE_SYNC  (1 << 2)
0187 #define DRM_EDID_INPUT_SEPARATE_SYNCS  (1 << 3)
0188 #define DRM_EDID_INPUT_BLANK_TO_BLACK  (1 << 4)
0189 #define DRM_EDID_INPUT_VIDEO_LEVEL     (3 << 5)
0190 #define DRM_EDID_INPUT_DIGITAL         (1 << 7)
0191 #define DRM_EDID_DIGITAL_DEPTH_MASK    (7 << 4) /* 1.4 */
0192 #define DRM_EDID_DIGITAL_DEPTH_UNDEF   (0 << 4) /* 1.4 */
0193 #define DRM_EDID_DIGITAL_DEPTH_6       (1 << 4) /* 1.4 */
0194 #define DRM_EDID_DIGITAL_DEPTH_8       (2 << 4) /* 1.4 */
0195 #define DRM_EDID_DIGITAL_DEPTH_10      (3 << 4) /* 1.4 */
0196 #define DRM_EDID_DIGITAL_DEPTH_12      (4 << 4) /* 1.4 */
0197 #define DRM_EDID_DIGITAL_DEPTH_14      (5 << 4) /* 1.4 */
0198 #define DRM_EDID_DIGITAL_DEPTH_16      (6 << 4) /* 1.4 */
0199 #define DRM_EDID_DIGITAL_DEPTH_RSVD    (7 << 4) /* 1.4 */
0200 #define DRM_EDID_DIGITAL_TYPE_MASK     (7 << 0) /* 1.4 */
0201 #define DRM_EDID_DIGITAL_TYPE_UNDEF    (0 << 0) /* 1.4 */
0202 #define DRM_EDID_DIGITAL_TYPE_DVI      (1 << 0) /* 1.4 */
0203 #define DRM_EDID_DIGITAL_TYPE_HDMI_A   (2 << 0) /* 1.4 */
0204 #define DRM_EDID_DIGITAL_TYPE_HDMI_B   (3 << 0) /* 1.4 */
0205 #define DRM_EDID_DIGITAL_TYPE_MDDI     (4 << 0) /* 1.4 */
0206 #define DRM_EDID_DIGITAL_TYPE_DP       (5 << 0) /* 1.4 */
0207 #define DRM_EDID_DIGITAL_DFP_1_X       (1 << 0) /* 1.3 */
0208
0209 #define DRM_EDID_FEATURE_DEFAULT_GTF      (1 << 0)
0210 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
0211 #define DRM_EDID_FEATURE_STANDARD_COLOR   (1 << 2)
0212 /* If analog */
0213 #define DRM_EDID_FEATURE_DISPLAY_TYPE     (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
0214 /* If digital */
0215 #define DRM_EDID_FEATURE_COLOR_MASK   (3 << 3)
0216 #define DRM_EDID_FEATURE_RGB          (0 << 3)
0217 #define DRM_EDID_FEATURE_RGB_YCRCB444     (1 << 3)
0218 #define DRM_EDID_FEATURE_RGB_YCRCB422     (2 << 3)
0219 #define DRM_EDID_FEATURE_RGB_YCRCB    (3 << 3) /* both 4:4:4 and 4:2:2 */
0220
0221 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF    (1 << 5)
0222 #define DRM_EDID_FEATURE_PM_SUSPEND       (1 << 6)
0223 #define DRM_EDID_FEATURE_PM_STANDBY       (1 << 7)
0224
0225 #define DRM_EDID_HDMI_DC_48               (1 << 6)
0226 #define DRM_EDID_HDMI_DC_36               (1 << 5)
0227 #define DRM_EDID_HDMI_DC_30               (1 << 4)
0228 #define DRM_EDID_HDMI_DC_Y444             (1 << 3)
0229
0230 /* YCBCR 420 deep color modes */
0231 #define DRM_EDID_YCBCR420_DC_48       (1 << 2)
0232 #define DRM_EDID_YCBCR420_DC_36       (1 << 1)
0233 #define DRM_EDID_YCBCR420_DC_30       (1 << 0)
0234 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \
0235                     DRM_EDID_YCBCR420_DC_36 | \
0236                     DRM_EDID_YCBCR420_DC_30)
0237
0238 /* HDMI 2.1 additional fields */
0239 #define DRM_EDID_MAX_FRL_RATE_MASK      0xf0
0240 #define DRM_EDID_FAPA_START_LOCATION        (1 << 0)
0241 #define DRM_EDID_ALLM               (1 << 1)
0242 #define DRM_EDID_FVA                (1 << 2)
0243
0244 /* Deep Color specific */
0245 #define DRM_EDID_DC_30BIT_420           (1 << 0)
0246 #define DRM_EDID_DC_36BIT_420           (1 << 1)
0247 #define DRM_EDID_DC_48BIT_420           (1 << 2)
0248
0249 /* VRR specific */
0250 #define DRM_EDID_CNMVRR             (1 << 3)
0251 #define DRM_EDID_CINEMA_VRR         (1 << 4)
0252 #define DRM_EDID_MDELTA             (1 << 5)
0253 #define DRM_EDID_VRR_MAX_UPPER_MASK     0xc0
0254 #define DRM_EDID_VRR_MAX_LOWER_MASK     0xff
0255 #define DRM_EDID_VRR_MIN_MASK           0x3f
0256
0257 /* DSC specific */
0258 #define DRM_EDID_DSC_10BPC          (1 << 0)
0259 #define DRM_EDID_DSC_12BPC          (1 << 1)
0260 #define DRM_EDID_DSC_16BPC          (1 << 2)
0261 #define DRM_EDID_DSC_ALL_BPP            (1 << 3)
0262 #define DRM_EDID_DSC_NATIVE_420         (1 << 6)
0263 #define DRM_EDID_DSC_1P2            (1 << 7)
0264 #define DRM_EDID_DSC_MAX_FRL_RATE_MASK      0xf0
0265 #define DRM_EDID_DSC_MAX_SLICES         0xf
0266 #define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES     0x3f
0267
0268 /* ELD Header Block */
0269 #define DRM_ELD_HEADER_BLOCK_SIZE   4
0270
0271 #define DRM_ELD_VER         0
0272 # define DRM_ELD_VER_SHIFT      3
0273 # define DRM_ELD_VER_MASK       (0x1f << 3)
0274 # define DRM_ELD_VER_CEA861D        (2 << 3) /* supports 861D or below */
0275 # define DRM_ELD_VER_CANNED     (0x1f << 3)
0276
0277 #define DRM_ELD_BASELINE_ELD_LEN    2   /* in dwords! */
0278
0279 /* ELD Baseline Block for ELD_Ver == 2 */
0280 #define DRM_ELD_CEA_EDID_VER_MNL    4
0281 # define DRM_ELD_CEA_EDID_VER_SHIFT 5
0282 # define DRM_ELD_CEA_EDID_VER_MASK  (7 << 5)
0283 # define DRM_ELD_CEA_EDID_VER_NONE  (0 << 5)
0284 # define DRM_ELD_CEA_EDID_VER_CEA861    (1 << 5)
0285 # define DRM_ELD_CEA_EDID_VER_CEA861A   (2 << 5)
0286 # define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5)
0287 # define DRM_ELD_MNL_SHIFT      0
0288 # define DRM_ELD_MNL_MASK       (0x1f << 0)
0289
0290 #define DRM_ELD_SAD_COUNT_CONN_TYPE 5
0291 # define DRM_ELD_SAD_COUNT_SHIFT    4
0292 # define DRM_ELD_SAD_COUNT_MASK     (0xf << 4)
0293 # define DRM_ELD_CONN_TYPE_SHIFT    2
0294 # define DRM_ELD_CONN_TYPE_MASK     (3 << 2)
0295 # define DRM_ELD_CONN_TYPE_HDMI     (0 << 2)
0296 # define DRM_ELD_CONN_TYPE_DP       (1 << 2)
0297 # define DRM_ELD_SUPPORTS_AI        (1 << 1)
0298 # define DRM_ELD_SUPPORTS_HDCP      (1 << 0)
0299
0300 #define DRM_ELD_AUD_SYNCH_DELAY     6   /* in units of 2 ms */
0301 # define DRM_ELD_AUD_SYNCH_DELAY_MAX    0xfa    /* 500 ms */
0302
0303 #define DRM_ELD_SPEAKER         7
0304 # define DRM_ELD_SPEAKER_MASK       0x7f
0305 # define DRM_ELD_SPEAKER_RLRC       (1 << 6)
0306 # define DRM_ELD_SPEAKER_FLRC       (1 << 5)
0307 # define DRM_ELD_SPEAKER_RC     (1 << 4)
0308 # define DRM_ELD_SPEAKER_RLR        (1 << 3)
0309 # define DRM_ELD_SPEAKER_FC     (1 << 2)
0310 # define DRM_ELD_SPEAKER_LFE        (1 << 1)
0311 # define DRM_ELD_SPEAKER_FLR        (1 << 0)
0312
0313 #define DRM_ELD_PORT_ID         8   /* offsets 8..15 inclusive */
0314 # define DRM_ELD_PORT_ID_LEN        8
0315
0316 #define DRM_ELD_MANUFACTURER_NAME0  16
0317 #define DRM_ELD_MANUFACTURER_NAME1  17
0318
0319 #define DRM_ELD_PRODUCT_CODE0       18
0320 #define DRM_ELD_PRODUCT_CODE1       19
0321
0322 #define DRM_ELD_MONITOR_NAME_STRING 20  /* offsets 20..(20+mnl-1) inclusive */
0323
0324 #define DRM_ELD_CEA_SAD(mnl, sad)   (20 + (mnl) + 3 * (sad))
0325
0326 struct edid {
0327     u8 header[8];
0328     /* Vendor & product info */
0329     u8 mfg_id[2];
0330     u8 prod_code[2];
0331     u32 serial; /* FIXME: byte order */
0332     u8 mfg_week;
0333     u8 mfg_year;
0334     /* EDID version */
0335     u8 version;
0336     u8 revision;
0337     /* Display info: */
0338     u8 input;
0339     u8 width_cm;
0340     u8 height_cm;
0341     u8 gamma;
0342     u8 features;
0343     /* Color characteristics */
0344     u8 red_green_lo;
0345     u8 blue_white_lo;
0346     u8 red_x;
0347     u8 red_y;
0348     u8 green_x;
0349     u8 green_y;
0350     u8 blue_x;
0351     u8 blue_y;
0352     u8 white_x;
0353     u8 white_y;
0354     /* Est. timings and mfg rsvd timings*/
0355     struct est_timings established_timings;
0356     /* Standard timings 1-8*/
0357     struct std_timing standard_timings[8];
0358     /* Detailing timings 1-4 */
0359     struct detailed_timing detailed_timings[4];
0360     /* Number of 128 byte ext. blocks */
0361     u8 extensions;
0362     /* Checksum */
0363     u8 checksum;
0364 } __attribute__((packed));
0365
0366 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
0367
0368 /* Short Audio Descriptor */
0369 struct cea_sad {
0370     u8 format;
0371     u8 channels; /* max number of channels - 1 */
0372     u8 freq;
0373     u8 byte2; /* meaning depends on format */
0374 };
0375
0376 struct drm_encoder;
0377 struct drm_connector;
0378 struct drm_connector_state;
0379 struct drm_display_mode;
0380
0381 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads);
0382 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb);
0383 int drm_av_sync_delay(struct drm_connector *connector,
0384               const struct drm_display_mode *mode);
0385
0386 #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
0387 struct edid *drm_load_edid_firmware(struct drm_connector *connector);
0388 int __drm_set_edid_firmware_path(const char *path);
0389 int __drm_get_edid_firmware_path(char *buf, size_t bufsize);
0390 #else
0391 static inline struct edid *
0392 drm_load_edid_firmware(struct drm_connector *connector)
0393 {
0394     return ERR_PTR(-ENOENT);
0395 }
0396 #endif
0397
0398 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2);
0399
0400 int
0401 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
0402                      const struct drm_connector *connector,
0403                      const struct drm_display_mode *mode);
0404 int
0405 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
0406                         const struct drm_connector *connector,
0407                         const struct drm_display_mode *mode);
0408
0409 void
0410 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
0411                    const struct drm_connector *connector,
0412                    const struct drm_display_mode *mode,
0413                    enum hdmi_quantization_range rgb_quant_range);
0414
0415 /**
0416  * drm_eld_mnl - Get ELD monitor name length in bytes.
0417  * @eld: pointer to an eld memory structure with mnl set
0418  */
0419 static inline int drm_eld_mnl(const uint8_t *eld)
0420 {
0421     return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT;
0422 }
0423
0424 /**
0425  * drm_eld_sad - Get ELD SAD structures.
0426  * @eld: pointer to an eld memory structure with sad_count set
0427  */
0428 static inline const uint8_t *drm_eld_sad(const uint8_t *eld)
0429 {
0430     unsigned int ver, mnl;
0431
0432     ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT;
0433     if (ver != 2 && ver != 31)
0434         return NULL;
0435
0436     mnl = drm_eld_mnl(eld);
0437     if (mnl > 16)
0438         return NULL;
0439
0440     return eld + DRM_ELD_CEA_SAD(mnl, 0);
0441 }
0442
0443 /**
0444  * drm_eld_sad_count - Get ELD SAD count.
0445  * @eld: pointer to an eld memory structure with sad_count set
0446  */
0447 static inline int drm_eld_sad_count(const uint8_t *eld)
0448 {
0449     return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >>
0450         DRM_ELD_SAD_COUNT_SHIFT;
0451 }
0452
0453 /**
0454  * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes
0455  * @eld: pointer to an eld memory structure with mnl and sad_count set
0456  *
0457  * This is a helper for determining the payload size of the baseline block, in
0458  * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block.
0459  */
0460 static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld)
0461 {
0462     return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE +
0463         drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3;
0464 }
0465
0466 /**
0467  * drm_eld_size - Get ELD size in bytes
0468  * @eld: pointer to a complete eld memory structure
0469  *
0470  * The returned value does not include the vendor block. It's vendor specific,
0471  * and comprises of the remaining bytes in the ELD memory buffer after
0472  * drm_eld_size() bytes of header and baseline block.
0473  *
0474  * The returned value is guaranteed to be a multiple of 4.
0475  */
0476 static inline int drm_eld_size(const uint8_t *eld)
0477 {
0478     return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4;
0479 }
0480
0481 /**
0482  * drm_eld_get_spk_alloc - Get speaker allocation
0483  * @eld: pointer to an ELD memory structure
0484  *
0485  * The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER
0486  * field definitions to identify speakers.
0487  */
0488 static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld)
0489 {
0490     return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK;
0491 }
0492
0493 /**
0494  * drm_eld_get_conn_type - Get device type hdmi/dp connected
0495  * @eld: pointer to an ELD memory structure
0496  *
0497  * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to
0498  * identify the display type connected.
0499  */
0500 static inline u8 drm_eld_get_conn_type(const uint8_t *eld)
0501 {
0502     return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK;
0503 }
0504
0505 /**
0506  * drm_edid_decode_mfg_id - Decode the manufacturer ID
0507  * @mfg_id: The manufacturer ID
0508  * @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0'
0509  *    termination
0510  */
0511 static inline const char *drm_edid_decode_mfg_id(u16 mfg_id, char vend[4])
0512 {
0513     vend[0] = '@' + ((mfg_id >> 10) & 0x1f);
0514     vend[1] = '@' + ((mfg_id >> 5) & 0x1f);
0515     vend[2] = '@' + ((mfg_id >> 0) & 0x1f);
0516     vend[3] = '\0';
0517
0518     return vend;
0519 }
0520
0521 /**
0522  * drm_edid_encode_panel_id - Encode an ID for matching against drm_edid_get_panel_id()
0523  * @vend_chr_0: First character of the vendor string.
0524  * @vend_chr_1: Second character of the vendor string.
0525  * @vend_chr_2: Third character of the vendor string.
0526  * @product_id: The 16-bit product ID.
0527  *
0528  * This is a macro so that it can be calculated at compile time and used
0529  * as an initializer.
0530  *
0531  * For instance:
0532  *   drm_edid_encode_panel_id('B', 'O', 'E', 0x2d08) => 0x09e52d08
0533  *
0534  * Return: a 32-bit ID per panel.
0535  */
0536 #define drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, product_id) \
0537     ((((u32)(vend_chr_0) - '@') & 0x1f) << 26 | \
0538      (((u32)(vend_chr_1) - '@') & 0x1f) << 21 | \
0539      (((u32)(vend_chr_2) - '@') & 0x1f) << 16 | \
0540      ((product_id) & 0xffff))
0541
0542 /**
0543  * drm_edid_decode_panel_id - Decode a panel ID from drm_edid_encode_panel_id()
0544  * @panel_id: The panel ID to decode.
0545  * @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0'
0546  *    termination
0547  * @product_id: The product ID will be returned here.
0548  *
0549  * For instance, after:
0550  *   drm_edid_decode_panel_id(0x09e52d08, vend, &product_id)
0551  * These will be true:
0552  *   vend[0] = 'B'
0553  *   vend[1] = 'O'
0554  *   vend[2] = 'E'
0555  *   vend[3] = '\0'
0556  *   product_id = 0x2d08
0557  */
0558 static inline void drm_edid_decode_panel_id(u32 panel_id, char vend[4], u16 *product_id)
0559 {
0560     *product_id = (u16)(panel_id & 0xffff);
0561     drm_edid_decode_mfg_id(panel_id >> 16, vend);
0562 }
0563
0564 bool drm_probe_ddc(struct i2c_adapter *adapter);
0565 struct edid *drm_do_get_edid(struct drm_connector *connector,
0566     int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
0567                   size_t len),
0568     void *data);
0569 struct edid *drm_get_edid(struct drm_connector *connector,
0570               struct i2c_adapter *adapter);
0571 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter);
0572 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
0573                      struct i2c_adapter *adapter);
0574 struct edid *drm_edid_duplicate(const struct edid *edid);
0575 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid);
0576 int drm_add_override_edid_modes(struct drm_connector *connector);
0577
0578 u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
0579 bool drm_detect_hdmi_monitor(const struct edid *edid);
0580 bool drm_detect_monitor_audio(const struct edid *edid);
0581 enum hdmi_quantization_range
0582 drm_default_rgb_quant_range(const struct drm_display_mode *mode);
0583 int drm_add_modes_noedid(struct drm_connector *connector,
0584              int hdisplay, int vdisplay);
0585 void drm_set_preferred_mode(struct drm_connector *connector,
0586                 int hpref, int vpref);
0587
0588 int drm_edid_header_is_valid(const void *edid);
0589 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
0590               bool *edid_corrupt);
0591 bool drm_edid_is_valid(struct edid *edid);
0592 void drm_edid_get_monitor_name(const struct edid *edid, char *name,
0593                    int buflen);
0594 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
0595                        int hsize, int vsize, int fresh,
0596                        bool rb);
0597 struct drm_display_mode *
0598 drm_display_mode_from_cea_vic(struct drm_device *dev,
0599                   u8 video_code);
0600
0601 /* Interface based on struct drm_edid */
0602 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size);
0603 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid);
0604 void drm_edid_free(const struct drm_edid *drm_edid);
0605 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid);
0606 const struct drm_edid *drm_edid_read(struct drm_connector *connector);
0607 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
0608                      struct i2c_adapter *adapter);
0609 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
0610                         int (*read_block)(void *context, u8 *buf, unsigned int block, size_t len),
0611                         void *context);
0612 int drm_edid_connector_update(struct drm_connector *connector,
0613                   const struct drm_edid *edid);
0614 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
0615                   int ext_id, int *ext_index);
0616
0617 #endif /* __DRM_EDID_H__ */