include/drm/drm_cache.h

0001 /**************************************************************************
0002  *
0003  * Copyright 2009 Red Hat Inc.
0004  * All Rights Reserved.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the
0008  * "Software"), to deal in the Software without restriction, including
0009  * without limitation the rights to use, copy, modify, merge, publish,
0010  * distribute, sub license, and/or sell copies of the Software, and to
0011  * permit persons to whom the Software is furnished to do so, subject to
0012  * the following conditions:
0013  *
0014  * The above copyright notice and this permission notice (including the
0015  * next paragraph) shall be included in all copies or substantial portions
0016  * of the Software.
0017  *
0018  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0019  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0020  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
0021  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
0022  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
0023  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
0024  * USE OR OTHER DEALINGS IN THE SOFTWARE.
0025  *
0026  *
0027  **************************************************************************/
0028 /*
0029  * Authors:
0030  * Dave Airlie <airlied@redhat.com>
0031  */
0032
0033 #ifndef _DRM_CACHE_H_
0034 #define _DRM_CACHE_H_
0035
0036 #include <linux/scatterlist.h>
0037
0038 struct iosys_map;
0039
0040 void drm_clflush_pages(struct page *pages[], unsigned long num_pages);
0041 void drm_clflush_sg(struct sg_table *st);
0042 void drm_clflush_virt_range(void *addr, unsigned long length);
0043 bool drm_need_swiotlb(int dma_bits);
0044
0045
0046 static inline bool drm_arch_can_wc_memory(void)
0047 {
0048 #if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
0049     return false;
0050 #elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON64)
0051     return false;
0052 #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64)
0053     /*
0054      * The DRM driver stack is designed to work with cache coherent devices
0055      * only, but permits an optimization to be enabled in some cases, where
0056      * for some buffers, both the CPU and the GPU use uncached mappings,
0057      * removing the need for DMA snooping and allocation in the CPU caches.
0058      *
0059      * The use of uncached GPU mappings relies on the correct implementation
0060      * of the PCIe NoSnoop TLP attribute by the platform, otherwise the GPU
0061      * will use cached mappings nonetheless. On x86 platforms, this does not
0062      * seem to matter, as uncached CPU mappings will snoop the caches in any
0063      * case. However, on ARM and arm64, enabling this optimization on a
0064      * platform where NoSnoop is ignored results in loss of coherency, which
0065      * breaks correct operation of the device. Since we have no way of
0066      * detecting whether NoSnoop works or not, just disable this
0067      * optimization entirely for ARM and arm64.
0068      */
0069     return false;
0070 #elif defined(CONFIG_LOONGARCH)
0071     /*
0072      * LoongArch maintains cache coherency in hardware, but its WUC attribute
0073      * (Weak-ordered UnCached, which is similar to WC) is out of the scope of
0074      * cache coherency machanism. This means WUC can only used for write-only
0075      * memory regions.
0076      */
0077     return false;
0078 #else
0079     return true;
0080 #endif
0081 }
0082
0083 void drm_memcpy_init_early(void);
0084
0085 void drm_memcpy_from_wc(struct iosys_map *dst,
0086             const struct iosys_map *src,
0087             unsigned long len);
0088 #endif