drm/display/drm_scdc.h

0001 /*
0002  * Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sub license,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the
0012  * next paragraph) shall be included in all copies or substantial portions
0013  * of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0020  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0021  * DEALINGS IN THE SOFTWARE.
0022  */
0023
0024 #ifndef DRM_SCDC_H
0025 #define DRM_SCDC_H
0026
0027 #define SCDC_SINK_VERSION 0x01
0028
0029 #define SCDC_SOURCE_VERSION 0x02
0030
0031 #define SCDC_UPDATE_0 0x10
0032 #define  SCDC_READ_REQUEST_TEST (1 << 2)
0033 #define  SCDC_CED_UPDATE (1 << 1)
0034 #define  SCDC_STATUS_UPDATE (1 << 0)
0035
0036 #define SCDC_UPDATE_1 0x11
0037
0038 #define SCDC_TMDS_CONFIG 0x20
0039 #define  SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 (1 << 1)
0040 #define  SCDC_TMDS_BIT_CLOCK_RATIO_BY_10 (0 << 1)
0041 #define  SCDC_SCRAMBLING_ENABLE (1 << 0)
0042
0043 #define SCDC_SCRAMBLER_STATUS 0x21
0044 #define  SCDC_SCRAMBLING_STATUS (1 << 0)
0045
0046 #define SCDC_CONFIG_0 0x30
0047 #define  SCDC_READ_REQUEST_ENABLE (1 << 0)
0048
0049 #define SCDC_STATUS_FLAGS_0 0x40
0050 #define  SCDC_CH2_LOCK (1 << 3)
0051 #define  SCDC_CH1_LOCK (1 << 2)
0052 #define  SCDC_CH0_LOCK (1 << 1)
0053 #define  SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK)
0054 #define  SCDC_CLOCK_DETECT (1 << 0)
0055
0056 #define SCDC_STATUS_FLAGS_1 0x41
0057
0058 #define SCDC_ERR_DET_0_L 0x50
0059 #define SCDC_ERR_DET_0_H 0x51
0060 #define SCDC_ERR_DET_1_L 0x52
0061 #define SCDC_ERR_DET_1_H 0x53
0062 #define SCDC_ERR_DET_2_L 0x54
0063 #define SCDC_ERR_DET_2_H 0x55
0064 #define  SCDC_CHANNEL_VALID (1 << 7)
0065
0066 #define SCDC_ERR_DET_CHECKSUM 0x56
0067
0068 #define SCDC_TEST_CONFIG_0 0xc0
0069 #define  SCDC_TEST_READ_REQUEST (1 << 7)
0070 #define  SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f)
0071
0072 #define SCDC_MANUFACTURER_IEEE_OUI 0xd0
0073 #define SCDC_MANUFACTURER_IEEE_OUI_SIZE 3
0074
0075 #define SCDC_DEVICE_ID 0xd3
0076 #define SCDC_DEVICE_ID_SIZE 8
0077
0078 #define SCDC_DEVICE_HARDWARE_REVISION 0xdb
0079 #define  SCDC_GET_DEVICE_HARDWARE_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
0080 #define  SCDC_GET_DEVICE_HARDWARE_REVISION_MINOR(x) (((x) >> 0) & 0xf)
0081
0082 #define SCDC_DEVICE_SOFTWARE_MAJOR_REVISION 0xdc
0083 #define SCDC_DEVICE_SOFTWARE_MINOR_REVISION 0xdd
0084
0085 #define SCDC_MANUFACTURER_SPECIFIC 0xde
0086 #define SCDC_MANUFACTURER_SPECIFIC_SIZE 34
0087
0088 #endif