drm/display/drm_hdcp.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright (C) 2017 Google, Inc.
0004  *
0005  * Authors:
0006  * Sean Paul <seanpaul@chromium.org>
0007  */
0008
0009 #ifndef _DRM_HDCP_H_
0010 #define _DRM_HDCP_H_
0011
0012 #include <linux/types.h>
0013
0014 /* Period of hdcp checks (to ensure we're still authenticated) */
0015 #define DRM_HDCP_CHECK_PERIOD_MS        (128 * 16)
0016 #define DRM_HDCP2_CHECK_PERIOD_MS       500
0017
0018 /* Shared lengths/masks between HDMI/DVI/DisplayPort */
0019 #define DRM_HDCP_AN_LEN             8
0020 #define DRM_HDCP_BSTATUS_LEN            2
0021 #define DRM_HDCP_KSV_LEN            5
0022 #define DRM_HDCP_RI_LEN             2
0023 #define DRM_HDCP_V_PRIME_PART_LEN       4
0024 #define DRM_HDCP_V_PRIME_NUM_PARTS      5
0025 #define DRM_HDCP_NUM_DOWNSTREAM(x)      (x & 0x7f)
0026 #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x)    (x & BIT(3))
0027 #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x)     (x & BIT(7))
0028
0029 /* Slave address for the HDCP registers in the receiver */
0030 #define DRM_HDCP_DDC_ADDR           0x3A
0031
0032 /* Value to use at the end of the SHA-1 bytestream used for repeaters */
0033 #define DRM_HDCP_SHA1_TERMINATOR        0x80
0034
0035 /* HDCP register offsets for HDMI/DVI devices */
0036 #define DRM_HDCP_DDC_BKSV           0x00
0037 #define DRM_HDCP_DDC_RI_PRIME           0x08
0038 #define DRM_HDCP_DDC_AKSV           0x10
0039 #define DRM_HDCP_DDC_AN             0x18
0040 #define DRM_HDCP_DDC_V_PRIME(h)         (0x20 + h * 4)
0041 #define DRM_HDCP_DDC_BCAPS          0x40
0042 #define  DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT    BIT(6)
0043 #define  DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY  BIT(5)
0044 #define DRM_HDCP_DDC_BSTATUS            0x41
0045 #define DRM_HDCP_DDC_KSV_FIFO           0x43
0046
0047 #define DRM_HDCP_1_4_SRM_ID         0x8
0048 #define DRM_HDCP_1_4_VRL_LENGTH_SIZE        3
0049 #define DRM_HDCP_1_4_DCP_SIG_SIZE       40
0050
0051 /* Protocol message definition for HDCP2.2 specification */
0052 /*
0053  * Protected content streams are classified into 2 types:
0054  * - Type0: Can be transmitted with HDCP 1.4+
0055  * - Type1: Can be transmitted with HDCP 2.2+
0056  */
0057 #define HDCP_STREAM_TYPE0           0x00
0058 #define HDCP_STREAM_TYPE1           0x01
0059
0060 /* HDCP2.2 Msg IDs */
0061 #define HDCP_2_2_NULL_MSG           1
0062 #define HDCP_2_2_AKE_INIT           2
0063 #define HDCP_2_2_AKE_SEND_CERT          3
0064 #define HDCP_2_2_AKE_NO_STORED_KM       4
0065 #define HDCP_2_2_AKE_STORED_KM          5
0066 #define HDCP_2_2_AKE_SEND_HPRIME        7
0067 #define HDCP_2_2_AKE_SEND_PAIRING_INFO      8
0068 #define HDCP_2_2_LC_INIT            9
0069 #define HDCP_2_2_LC_SEND_LPRIME         10
0070 #define HDCP_2_2_SKE_SEND_EKS           11
0071 #define HDCP_2_2_REP_SEND_RECVID_LIST       12
0072 #define HDCP_2_2_REP_SEND_ACK           15
0073 #define HDCP_2_2_REP_STREAM_MANAGE      16
0074 #define HDCP_2_2_REP_STREAM_READY       17
0075
0076 #define HDCP_2_2_RTX_LEN            8
0077 #define HDCP_2_2_RRX_LEN            8
0078
0079 #define HDCP_2_2_K_PUB_RX_MOD_N_LEN     128
0080 #define HDCP_2_2_K_PUB_RX_EXP_E_LEN     3
0081 #define HDCP_2_2_K_PUB_RX_LEN           (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \
0082                          HDCP_2_2_K_PUB_RX_EXP_E_LEN)
0083
0084 #define HDCP_2_2_DCP_LLC_SIG_LEN        384
0085
0086 #define HDCP_2_2_E_KPUB_KM_LEN          128
0087 #define HDCP_2_2_E_KH_KM_M_LEN          (16 + 16)
0088 #define HDCP_2_2_H_PRIME_LEN            32
0089 #define HDCP_2_2_E_KH_KM_LEN            16
0090 #define HDCP_2_2_RN_LEN             8
0091 #define HDCP_2_2_L_PRIME_LEN            32
0092 #define HDCP_2_2_E_DKEY_KS_LEN          16
0093 #define HDCP_2_2_RIV_LEN            8
0094 #define HDCP_2_2_SEQ_NUM_LEN            3
0095 #define HDCP_2_2_V_PRIME_HALF_LEN       (HDCP_2_2_L_PRIME_LEN / 2)
0096 #define HDCP_2_2_RECEIVER_ID_LEN        DRM_HDCP_KSV_LEN
0097 #define HDCP_2_2_MAX_DEVICE_COUNT       31
0098 #define HDCP_2_2_RECEIVER_IDS_MAX_LEN       (HDCP_2_2_RECEIVER_ID_LEN * \
0099                          HDCP_2_2_MAX_DEVICE_COUNT)
0100 #define HDCP_2_2_MPRIME_LEN         32
0101
0102 /* Following Macros take a byte at a time for bit(s) masking */
0103 /*
0104  * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual
0105  * H/W MST streams capacity.
0106  * This required to be moved out to platform specific header.
0107  */
0108 #define HDCP_2_2_MAX_CONTENT_STREAMS_CNT    4
0109 #define HDCP_2_2_TXCAP_MASK_LEN         2
0110 #define HDCP_2_2_RXCAPS_LEN         3
0111 #define HDCP_2_2_RX_REPEATER(x)         ((x) & BIT(0))
0112 #define HDCP_2_2_DP_HDCP_CAPABLE(x)     ((x) & BIT(1))
0113 #define HDCP_2_2_RXINFO_LEN         2
0114
0115 /* HDCP1.x compliant device in downstream */
0116 #define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x)  ((x) & BIT(0))
0117
0118 /* HDCP2.0 Compliant repeater in downstream */
0119 #define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x)  ((x) & BIT(1))
0120 #define HDCP_2_2_MAX_CASCADE_EXCEEDED(x)    ((x) & BIT(2))
0121 #define HDCP_2_2_MAX_DEVS_EXCEEDED(x)       ((x) & BIT(3))
0122 #define HDCP_2_2_DEV_COUNT_LO(x)        (((x) & (0xF << 4)) >> 4)
0123 #define HDCP_2_2_DEV_COUNT_HI(x)        ((x) & BIT(0))
0124 #define HDCP_2_2_DEPTH(x)           (((x) & (0x7 << 1)) >> 1)
0125
0126 struct hdcp2_cert_rx {
0127     u8  receiver_id[HDCP_2_2_RECEIVER_ID_LEN];
0128     u8  kpub_rx[HDCP_2_2_K_PUB_RX_LEN];
0129     u8  reserved[2];
0130     u8  dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN];
0131 } __packed;
0132
0133 struct hdcp2_streamid_type {
0134     u8  stream_id;
0135     u8  stream_type;
0136 } __packed;
0137
0138 /*
0139  * The TxCaps field specified in the HDCP HDMI, DP specs
0140  * This field is big endian as specified in the errata.
0141  */
0142 struct hdcp2_tx_caps {
0143     /* Transmitter must set this to 0x2 */
0144     u8  version;
0145
0146     /* Reserved for HDCP and DP Spec. Read as Zero */
0147     u8  tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN];
0148 } __packed;
0149
0150 /* Main structures for HDCP2.2 protocol communication */
0151 struct hdcp2_ake_init {
0152     u8          msg_id;
0153     u8          r_tx[HDCP_2_2_RTX_LEN];
0154     struct hdcp2_tx_caps    tx_caps;
0155 } __packed;
0156
0157 struct hdcp2_ake_send_cert {
0158     u8          msg_id;
0159     struct hdcp2_cert_rx    cert_rx;
0160     u8          r_rx[HDCP_2_2_RRX_LEN];
0161     u8          rx_caps[HDCP_2_2_RXCAPS_LEN];
0162 } __packed;
0163
0164 struct hdcp2_ake_no_stored_km {
0165     u8  msg_id;
0166     u8  e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN];
0167 } __packed;
0168
0169 struct hdcp2_ake_stored_km {
0170     u8  msg_id;
0171     u8  e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN];
0172 } __packed;
0173
0174 struct hdcp2_ake_send_hprime {
0175     u8  msg_id;
0176     u8  h_prime[HDCP_2_2_H_PRIME_LEN];
0177 } __packed;
0178
0179 struct hdcp2_ake_send_pairing_info {
0180     u8  msg_id;
0181     u8  e_kh_km[HDCP_2_2_E_KH_KM_LEN];
0182 } __packed;
0183
0184 struct hdcp2_lc_init {
0185     u8  msg_id;
0186     u8  r_n[HDCP_2_2_RN_LEN];
0187 } __packed;
0188
0189 struct hdcp2_lc_send_lprime {
0190     u8  msg_id;
0191     u8  l_prime[HDCP_2_2_L_PRIME_LEN];
0192 } __packed;
0193
0194 struct hdcp2_ske_send_eks {
0195     u8  msg_id;
0196     u8  e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN];
0197     u8  riv[HDCP_2_2_RIV_LEN];
0198 } __packed;
0199
0200 struct hdcp2_rep_send_receiverid_list {
0201     u8  msg_id;
0202     u8  rx_info[HDCP_2_2_RXINFO_LEN];
0203     u8  seq_num_v[HDCP_2_2_SEQ_NUM_LEN];
0204     u8  v_prime[HDCP_2_2_V_PRIME_HALF_LEN];
0205     u8  receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN];
0206 } __packed;
0207
0208 struct hdcp2_rep_send_ack {
0209     u8  msg_id;
0210     u8  v[HDCP_2_2_V_PRIME_HALF_LEN];
0211 } __packed;
0212
0213 struct hdcp2_rep_stream_manage {
0214     u8          msg_id;
0215     u8          seq_num_m[HDCP_2_2_SEQ_NUM_LEN];
0216     __be16          k;
0217     struct hdcp2_streamid_type streams[HDCP_2_2_MAX_CONTENT_STREAMS_CNT];
0218 } __packed;
0219
0220 struct hdcp2_rep_stream_ready {
0221     u8  msg_id;
0222     u8  m_prime[HDCP_2_2_MPRIME_LEN];
0223 } __packed;
0224
0225 /* HDCP2.2 TIMEOUTs in mSec */
0226 #define HDCP_2_2_CERT_TIMEOUT_MS        100
0227 #define HDCP_2_2_DP_CERT_READ_TIMEOUT_MS    110
0228 #define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS    1000
0229 #define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS   200
0230 #define HDCP_2_2_DP_HPRIME_READ_TIMEOUT_MS  7
0231 #define HDCP_2_2_PAIRING_TIMEOUT_MS     200
0232 #define HDCP_2_2_DP_PAIRING_READ_TIMEOUT_MS 5
0233 #define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS     20
0234 #define HDCP_2_2_DP_LPRIME_TIMEOUT_MS       16
0235 #define HDCP_2_2_RECVID_LIST_TIMEOUT_MS     3000
0236 #define HDCP_2_2_STREAM_READY_TIMEOUT_MS    100
0237
0238 /* HDMI HDCP2.2 Register Offsets */
0239 #define HDCP_2_2_HDMI_REG_VER_OFFSET        0x50
0240 #define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET     0x60
0241 #define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET   0x70
0242 #define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET     0x80
0243 #define HDCP_2_2_HDMI_REG_DBG_OFFSET        0xC0
0244
0245 #define HDCP_2_2_HDMI_SUPPORT_MASK      BIT(2)
0246 #define HDCP_2_2_RX_CAPS_VERSION_VAL        0x02
0247 #define HDCP_2_2_SEQ_NUM_MAX            0xFFFFFF
0248 #define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200
0249
0250 /* Below macros take a byte at a time and mask the bit(s) */
0251 #define HDCP_2_2_HDMI_RXSTATUS_LEN      2
0252 #define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3)
0253 #define HDCP_2_2_HDMI_RXSTATUS_READY(x)     ((x) & BIT(2))
0254 #define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x)    ((x) & BIT(3))
0255
0256 /*
0257  * Helper functions to convert 24bit big endian hdcp sequence number to
0258  * host format and back
0259  */
0260 static inline
0261 u32 drm_hdcp_be24_to_cpu(const u8 seq_num[HDCP_2_2_SEQ_NUM_LEN])
0262 {
0263     return (u32)(seq_num[2] | seq_num[1] << 8 | seq_num[0] << 16);
0264 }
0265
0266 static inline
0267 void drm_hdcp_cpu_to_be24(u8 seq_num[HDCP_2_2_SEQ_NUM_LEN], u32 val)
0268 {
0269     seq_num[0] = val >> 16;
0270     seq_num[1] = val >> 8;
0271     seq_num[2] = val;
0272 }
0273
0274 #define DRM_HDCP_SRM_GEN1_MAX_BYTES     (5 * 1024)
0275 #define DRM_HDCP_1_4_SRM_ID         0x8
0276 #define DRM_HDCP_SRM_ID_MASK            (0xF << 4)
0277 #define DRM_HDCP_1_4_VRL_LENGTH_SIZE        3
0278 #define DRM_HDCP_1_4_DCP_SIG_SIZE       40
0279 #define DRM_HDCP_2_SRM_ID           0x9
0280 #define DRM_HDCP_2_INDICATOR            0x1
0281 #define DRM_HDCP_2_INDICATOR_MASK       0xF
0282 #define DRM_HDCP_2_VRL_LENGTH_SIZE      3
0283 #define DRM_HDCP_2_DCP_SIG_SIZE         384
0284 #define DRM_HDCP_2_NO_OF_DEV_PLUS_RESERVED_SZ   4
0285 #define DRM_HDCP_2_KSV_COUNT_2_LSBITS(byte) (((byte) & 0xC0) >> 6)
0286
0287 struct hdcp_srm_header {
0288     u8 srm_id;
0289     u8 reserved;
0290     __be16 srm_version;
0291     u8 srm_gen_no;
0292 } __packed;
0293
0294 /* Content Type classification for HDCP2.2 vs others */
0295 #define DRM_MODE_HDCP_CONTENT_TYPE0     0
0296 #define DRM_MODE_HDCP_CONTENT_TYPE1     1
0297
0298 #endif