drm/display/drm_dsc.h

0001 /* SPDX-License-Identifier: MIT
0002  * Copyright (C) 2018 Intel Corp.
0003  *
0004  * Authors:
0005  * Manasi Navare <manasi.d.navare@intel.com>
0006  */
0007
0008 #ifndef DRM_DSC_H_
0009 #define DRM_DSC_H_
0010
0011 #include <drm/display/drm_dp.h>
0012
0013 /* VESA Display Stream Compression DSC 1.2 constants */
0014 #define DSC_NUM_BUF_RANGES          15
0015 #define DSC_MUX_WORD_SIZE_8_10_BPC      48
0016 #define DSC_MUX_WORD_SIZE_12_BPC        64
0017 #define DSC_RC_PIXELS_PER_GROUP         3
0018 #define DSC_SCALE_DECREMENT_INTERVAL_MAX    4095
0019 #define DSC_RANGE_BPG_OFFSET_MASK       0x3f
0020
0021 /* DSC Rate Control Constants */
0022 #define DSC_RC_MODEL_SIZE_CONST         8192
0023 #define DSC_RC_EDGE_FACTOR_CONST        6
0024 #define DSC_RC_TGT_OFFSET_HI_CONST      3
0025 #define DSC_RC_TGT_OFFSET_LO_CONST      3
0026
0027 /* DSC PPS constants and macros */
0028 #define DSC_PPS_VERSION_MAJOR_SHIFT     4
0029 #define DSC_PPS_BPC_SHIFT           4
0030 #define DSC_PPS_MSB_SHIFT           8
0031 #define DSC_PPS_LSB_MASK            (0xFF << 0)
0032 #define DSC_PPS_BPP_HIGH_MASK           (0x3 << 8)
0033 #define DSC_PPS_VBR_EN_SHIFT            2
0034 #define DSC_PPS_SIMPLE422_SHIFT         3
0035 #define DSC_PPS_CONVERT_RGB_SHIFT       4
0036 #define DSC_PPS_BLOCK_PRED_EN_SHIFT     5
0037 #define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK   (0x3 << 8)
0038 #define DSC_PPS_SCALE_DEC_INT_HIGH_MASK     (0xF << 8)
0039 #define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT      4
0040 #define DSC_PPS_RC_RANGE_MINQP_SHIFT        11
0041 #define DSC_PPS_RC_RANGE_MAXQP_SHIFT        6
0042 #define DSC_PPS_NATIVE_420_SHIFT        1
0043 #define DSC_1_2_MAX_LINEBUF_DEPTH_BITS      16
0044 #define DSC_1_2_MAX_LINEBUF_DEPTH_VAL       0
0045 #define DSC_1_1_MAX_LINEBUF_DEPTH_BITS      13
0046
0047 /**
0048  * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
0049  *
0050  * This defines different rate control parameters used by the DSC engine
0051  * to compress the frame.
0052  */
0053 struct drm_dsc_rc_range_parameters {
0054     /**
0055      * @range_min_qp: Min Quantization Parameters allowed for this range
0056      */
0057     u8 range_min_qp;
0058     /**
0059      * @range_max_qp: Max Quantization Parameters allowed for this range
0060      */
0061     u8 range_max_qp;
0062     /**
0063      * @range_bpg_offset:
0064      * Bits/group offset to apply to target for this group
0065      */
0066     u8 range_bpg_offset;
0067 };
0068
0069 /**
0070  * struct drm_dsc_config - Parameters required to configure DSC
0071  *
0072  * Driver populates this structure with all the parameters required
0073  * to configure the display stream compression on the source.
0074  */
0075 struct drm_dsc_config {
0076     /**
0077      * @line_buf_depth:
0078      * Bits per component for previous reconstructed line buffer
0079      */
0080     u8 line_buf_depth;
0081     /**
0082      * @bits_per_component: Bits per component to code (8/10/12)
0083      */
0084     u8 bits_per_component;
0085     /**
0086      * @convert_rgb:
0087      * Flag to indicate if RGB - YCoCg conversion is needed
0088      * True if RGB input, False if YCoCg input
0089      */
0090     bool convert_rgb;
0091     /**
0092      * @slice_count: Number fo slices per line used by the DSC encoder
0093      */
0094     u8 slice_count;
0095     /**
0096      *  @slice_width: Width of each slice in pixels
0097      */
0098     u16 slice_width;
0099     /**
0100      * @slice_height: Slice height in pixels
0101      */
0102     u16 slice_height;
0103     /**
0104      * @simple_422: True if simple 4_2_2 mode is enabled else False
0105      */
0106     bool simple_422;
0107     /**
0108      * @pic_width: Width of the input display frame in pixels
0109      */
0110     u16 pic_width;
0111     /**
0112      * @pic_height: Vertical height of the input display frame
0113      */
0114     u16 pic_height;
0115     /**
0116      * @rc_tgt_offset_high:
0117      * Offset to bits/group used by RC to determine QP adjustment
0118      */
0119     u8 rc_tgt_offset_high;
0120     /**
0121      * @rc_tgt_offset_low:
0122      * Offset to bits/group used by RC to determine QP adjustment
0123      */
0124     u8 rc_tgt_offset_low;
0125     /**
0126      * @bits_per_pixel:
0127      * Target bits per pixel with 4 fractional bits, bits_per_pixel << 4
0128      */
0129     u16 bits_per_pixel;
0130     /**
0131      * @rc_edge_factor:
0132      * Factor to determine if an edge is present based on the bits produced
0133      */
0134     u8 rc_edge_factor;
0135     /**
0136      * @rc_quant_incr_limit1:
0137      * Slow down incrementing once the range reaches this value
0138      */
0139     u8 rc_quant_incr_limit1;
0140     /**
0141      * @rc_quant_incr_limit0:
0142      * Slow down incrementing once the range reaches this value
0143      */
0144     u8 rc_quant_incr_limit0;
0145     /**
0146      * @initial_xmit_delay:
0147      * Number of pixels to delay the initial transmission
0148      */
0149     u16 initial_xmit_delay;
0150     /**
0151      * @initial_dec_delay:
0152      * Initial decoder delay, number of pixel times that the decoder
0153      * accumulates data in its rate buffer before starting to decode
0154      * and output pixels.
0155      */
0156     u16  initial_dec_delay;
0157     /**
0158      * @block_pred_enable:
0159      * True if block prediction is used to code any groups within the
0160      * picture. False if BP not used
0161      */
0162     bool block_pred_enable;
0163     /**
0164      * @first_line_bpg_offset:
0165      * Number of additional bits allocated for each group on the first
0166      * line of slice.
0167      */
0168     u8 first_line_bpg_offset;
0169     /**
0170      * @initial_offset: Value to use for RC model offset at slice start
0171      */
0172     u16 initial_offset;
0173     /**
0174      * @rc_buf_thresh: Thresholds defining each of the buffer ranges
0175      */
0176     u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
0177     /**
0178      * @rc_range_params:
0179      * Parameters for each of the RC ranges defined in
0180      * &struct drm_dsc_rc_range_parameters
0181      */
0182     struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
0183     /**
0184      * @rc_model_size: Total size of RC model
0185      */
0186     u16 rc_model_size;
0187     /**
0188      * @flatness_min_qp: Minimum QP where flatness information is sent
0189      */
0190     u8 flatness_min_qp;
0191     /**
0192      * @flatness_max_qp: Maximum QP where flatness information is sent
0193      */
0194     u8 flatness_max_qp;
0195     /**
0196      * @initial_scale_value: Initial value for the scale factor
0197      */
0198     u8 initial_scale_value;
0199     /**
0200      * @scale_decrement_interval:
0201      * Specifies number of group times between decrementing the scale factor
0202      * at beginning of a slice.
0203      */
0204     u16 scale_decrement_interval;
0205     /**
0206      * @scale_increment_interval:
0207      * Number of group times between incrementing the scale factor value
0208      * used at the beginning of a slice.
0209      */
0210     u16 scale_increment_interval;
0211     /**
0212      * @nfl_bpg_offset: Non first line BPG offset to be used
0213      */
0214     u16 nfl_bpg_offset;
0215     /**
0216      * @slice_bpg_offset: BPG offset used to enforce slice bit
0217      */
0218     u16 slice_bpg_offset;
0219     /**
0220      * @final_offset: Final RC linear transformation offset value
0221      */
0222     u16 final_offset;
0223     /**
0224      * @vbr_enable: True if VBR mode is enabled, false if disabled
0225      */
0226     bool vbr_enable;
0227     /**
0228      * @mux_word_size: Mux word size (in bits) for SSM mode
0229      */
0230     u8 mux_word_size;
0231     /**
0232      * @slice_chunk_size:
0233      * The (max) size in bytes of the "chunks" that are used in slice
0234      * multiplexing.
0235      */
0236     u16 slice_chunk_size;
0237     /**
0238      * @rc_bits: Rate control buffer size in bits
0239      */
0240     u16 rc_bits;
0241     /**
0242      * @dsc_version_minor: DSC minor version
0243      */
0244     u8 dsc_version_minor;
0245     /**
0246      * @dsc_version_major: DSC major version
0247      */
0248     u8 dsc_version_major;
0249     /**
0250      * @native_422: True if Native 4:2:2 supported, else false
0251      */
0252     bool native_422;
0253     /**
0254      * @native_420: True if Native 4:2:0 supported else false.
0255      */
0256     bool native_420;
0257     /**
0258      * @second_line_bpg_offset:
0259      * Additional bits/grp for seconnd line of slice for native 4:2:0
0260      */
0261     u8 second_line_bpg_offset;
0262     /**
0263      * @nsl_bpg_offset:
0264      * Num of bits deallocated for each grp that is not in second line of
0265      * slice
0266      */
0267     u16 nsl_bpg_offset;
0268     /**
0269      * @second_line_offset_adj:
0270      * Offset adjustment for second line in Native 4:2:0 mode
0271      */
0272     u16 second_line_offset_adj;
0273 };
0274
0275 /**
0276  * struct drm_dsc_picture_parameter_set - Represents 128 bytes of
0277  *  Picture Parameter Set
0278  *
0279  * The VESA DSC standard defines picture parameter set (PPS) which display
0280  * stream compression encoders must communicate to decoders.
0281  * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
0282  * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
0283  * The PPS fields that span over more than a byte should be stored in Big Endian
0284  * format.
0285  */
0286 struct drm_dsc_picture_parameter_set {
0287     /**
0288      * @dsc_version:
0289      * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
0290      * PPS0[7:4] - dsc_version_major: Contains major version of DSC
0291      */
0292     u8 dsc_version;
0293     /**
0294      * @pps_identifier:
0295      * PPS1[7:0] - Application specific identifier that can be
0296      * used to differentiate between different PPS tables.
0297      */
0298     u8 pps_identifier;
0299     /**
0300      * @pps_reserved:
0301      * PPS2[7:0]- RESERVED Byte
0302      */
0303     u8 pps_reserved;
0304     /**
0305      * @pps_3:
0306      * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
0307      * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
0308      * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
0309      * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
0310      * PPS3[7:4] - bits_per_component: Bits per component for the original
0311      * pixels of the encoded picture.
0312      * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
0313      * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
0314      * allowed only when dsc_minor_version = 0x2)
0315      */
0316     u8 pps_3;
0317     /**
0318      * @pps_4:
0319      * PPS4[1:0] -These are the most significant 2 bits of
0320      * compressed BPP bits_per_pixel[9:0] syntax element.
0321      * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
0322      * PPS4[3] - simple_422: Indicates if decoder drops samples to
0323      * reconstruct the 4:2:2 picture.
0324      * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
0325      * active.
0326      * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
0327      * groups in picture
0328      * PPS4[7:6] - Reseved bits
0329      */
0330     u8 pps_4;
0331     /**
0332      * @bits_per_pixel_low:
0333      * PPS5[7:0] - This indicates the lower significant 8 bits of
0334      * the compressed BPP bits_per_pixel[9:0] element.
0335      */
0336     u8 bits_per_pixel_low;
0337     /**
0338      * @pic_height:
0339      * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
0340      * within the raster.
0341      */
0342     __be16 pic_height;
0343     /**
0344      * @pic_width:
0345      * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
0346      * the raster.
0347      */
0348     __be16 pic_width;
0349     /**
0350      * @slice_height:
0351      * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
0352      */
0353     __be16 slice_height;
0354     /**
0355      * @slice_width:
0356      * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
0357      */
0358     __be16 slice_width;
0359     /**
0360      * @chunk_size:
0361      * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
0362      * that are used for slice multiplexing.
0363      */
0364     __be16 chunk_size;
0365     /**
0366      * @initial_xmit_delay_high:
0367      * PPS16[1:0] - Most Significant two bits of initial transmission delay.
0368      * It specifies the number of pixel times that the encoder waits before
0369      * transmitting data from its rate buffer.
0370      * PPS16[7:2] - Reserved
0371      */
0372     u8 initial_xmit_delay_high;
0373     /**
0374      * @initial_xmit_delay_low:
0375      * PPS17[7:0] - Least significant 8 bits of initial transmission delay.
0376      */
0377     u8 initial_xmit_delay_low;
0378     /**
0379      * @initial_dec_delay:
0380      *
0381      * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number
0382      * of pixel times that the decoder accumulates data in its rate buffer
0383      * before starting to decode and output pixels.
0384      */
0385     __be16 initial_dec_delay;
0386     /**
0387      * @pps20_reserved:
0388      *
0389      * PPS20[7:0] - Reserved
0390      */
0391     u8 pps20_reserved;
0392     /**
0393      * @initial_scale_value:
0394      * PPS21[5:0] - Initial rcXformScale factor used at beginning
0395      * of a slice.
0396      * PPS21[7:6] - Reserved
0397      */
0398     u8 initial_scale_value;
0399     /**
0400      * @scale_increment_interval:
0401      * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing
0402      * the rcXformScale factor at end of a slice.
0403      */
0404     __be16 scale_increment_interval;
0405     /**
0406      * @scale_decrement_interval_high:
0407      * PPS24[3:0] - Higher 4 bits indicating number of group times between
0408      * decrementing the rcXformScale factor at beginning of a slice.
0409      * PPS24[7:4] - Reserved
0410      */
0411     u8 scale_decrement_interval_high;
0412     /**
0413      * @scale_decrement_interval_low:
0414      * PPS25[7:0] - Lower 8 bits of scale decrement interval
0415      */
0416     u8 scale_decrement_interval_low;
0417     /**
0418      * @pps26_reserved:
0419      * PPS26[7:0]
0420      */
0421     u8 pps26_reserved;
0422     /**
0423      * @first_line_bpg_offset:
0424      * PPS27[4:0] - Number of additional bits that are allocated
0425      * for each group on first line of a slice.
0426      * PPS27[7:5] - Reserved
0427      */
0428     u8 first_line_bpg_offset;
0429     /**
0430      * @nfl_bpg_offset:
0431      * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits
0432      * deallocated for each group for groups after the first line of slice.
0433      */
0434     __be16 nfl_bpg_offset;
0435     /**
0436      * @slice_bpg_offset:
0437      * PPS30, PPS31[7:0] - Number of bits that are deallocated for each
0438      * group to enforce the slice constraint.
0439      */
0440     __be16 slice_bpg_offset;
0441     /**
0442      * @initial_offset:
0443      * PPS32,33[7:0] - Initial value for rcXformOffset
0444      */
0445     __be16 initial_offset;
0446     /**
0447      * @final_offset:
0448      * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset
0449      */
0450     __be16 final_offset;
0451     /**
0452      * @flatness_min_qp:
0453      * PPS36[4:0] - Minimum QP at which flatness is signaled and
0454      * flatness QP adjustment is made.
0455      * PPS36[7:5] - Reserved
0456      */
0457     u8 flatness_min_qp;
0458     /**
0459      * @flatness_max_qp:
0460      * PPS37[4:0] - Max QP at which flatness is signalled and
0461      * the flatness adjustment is made.
0462      * PPS37[7:5] - Reserved
0463      */
0464     u8 flatness_max_qp;
0465     /**
0466      * @rc_model_size:
0467      * PPS38,39[7:0] - Number of bits within RC Model.
0468      */
0469     __be16 rc_model_size;
0470     /**
0471      * @rc_edge_factor:
0472      * PPS40[3:0] - Ratio of current activity vs, previous
0473      * activity to determine presence of edge.
0474      * PPS40[7:4] - Reserved
0475      */
0476     u8 rc_edge_factor;
0477     /**
0478      * @rc_quant_incr_limit0:
0479      * PPS41[4:0] - QP threshold used in short term RC
0480      * PPS41[7:5] - Reserved
0481      */
0482     u8 rc_quant_incr_limit0;
0483     /**
0484      * @rc_quant_incr_limit1:
0485      * PPS42[4:0] - QP threshold used in short term RC
0486      * PPS42[7:5] - Reserved
0487      */
0488     u8 rc_quant_incr_limit1;
0489     /**
0490      * @rc_tgt_offset:
0491      * PPS43[3:0] - Lower end of the variability range around the target
0492      * bits per group that is allowed by short term RC.
0493      * PPS43[7:4]- Upper end of the variability range around the target
0494      * bits per group that i allowed by short term rc.
0495      */
0496     u8 rc_tgt_offset;
0497     /**
0498      * @rc_buf_thresh:
0499      * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for
0500      * the 15 ranges defined by 14 thresholds.
0501      */
0502     u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
0503     /**
0504      * @rc_range_parameters:
0505      * PPS58[7:0] - PPS87[7:0]
0506      * Parameters that correspond to each of the 15 ranges.
0507      */
0508     __be16 rc_range_parameters[DSC_NUM_BUF_RANGES];
0509     /**
0510      * @native_422_420:
0511      * PPS88[0] - 0 = Native 4:2:2 not used
0512      * 1 = Native 4:2:2 used
0513      * PPS88[1] - 0 = Native 4:2:0 not use
0514      * 1 = Native 4:2:0 used
0515      * PPS88[7:2] - Reserved 6 bits
0516      */
0517     u8 native_422_420;
0518     /**
0519      * @second_line_bpg_offset:
0520      * PPS89[4:0] - Additional bits/group budget for the
0521      * second line of a slice in Native 4:2:0 mode.
0522      * Set to 0 if DSC minor version is 1 or native420 is 0.
0523      * PPS89[7:5] - Reserved
0524      */
0525     u8 second_line_bpg_offset;
0526     /**
0527      * @nsl_bpg_offset:
0528      * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated
0529      * for each group that is not in the second line of a slice.
0530      */
0531     __be16 nsl_bpg_offset;
0532     /**
0533      * @second_line_offset_adj:
0534      * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
0535      * line in Native 4:2:0 mode.
0536      */
0537     __be16 second_line_offset_adj;
0538     /**
0539      * @pps_long_94_reserved:
0540      * PPS 94, 95, 96, 97 - Reserved
0541      */
0542     u32 pps_long_94_reserved;
0543     /**
0544      * @pps_long_98_reserved:
0545      * PPS 98, 99, 100, 101 - Reserved
0546      */
0547     u32 pps_long_98_reserved;
0548     /**
0549      * @pps_long_102_reserved:
0550      * PPS 102, 103, 104, 105 - Reserved
0551      */
0552     u32 pps_long_102_reserved;
0553     /**
0554      * @pps_long_106_reserved:
0555      * PPS 106, 107, 108, 109 - reserved
0556      */
0557     u32 pps_long_106_reserved;
0558     /**
0559      * @pps_long_110_reserved:
0560      * PPS 110, 111, 112, 113 - reserved
0561      */
0562     u32 pps_long_110_reserved;
0563     /**
0564      * @pps_long_114_reserved:
0565      * PPS 114 - 117 - reserved
0566      */
0567     u32 pps_long_114_reserved;
0568     /**
0569      * @pps_long_118_reserved:
0570      * PPS 118 - 121 - reserved
0571      */
0572     u32 pps_long_118_reserved;
0573     /**
0574      * @pps_long_122_reserved:
0575      * PPS 122- 125 - reserved
0576      */
0577     u32 pps_long_122_reserved;
0578     /**
0579      * @pps_short_126_reserved:
0580      * PPS 126, 127 - reserved
0581      */
0582     __be16 pps_short_126_reserved;
0583 } __packed;
0584
0585 /**
0586  * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter
0587  * Set Metadata
0588  *
0589  * This structure represents the DSC PPS infoframe required to send the Picture
0590  * Parameter Set metadata required before enabling VESA Display Stream
0591  * Compression. This is based on the DP Secondary Data Packet structure and
0592  * comprises of SDP Header as defined &struct dp_sdp_header in drm_dp_helper.h
0593  * and PPS payload defined in &struct drm_dsc_picture_parameter_set.
0594  *
0595  * @pps_header: Header for PPS as per DP SDP header format of type
0596  *              &struct dp_sdp_header
0597  * @pps_payload: PPS payload fields as per DSC specification Table 4-1
0598  *               as represented in &struct drm_dsc_picture_parameter_set
0599  */
0600 struct drm_dsc_pps_infoframe {
0601     struct dp_sdp_header pps_header;
0602     struct drm_dsc_picture_parameter_set pps_payload;
0603 } __packed;
0604
0605 #endif /* _DRM_DSC_H_ */