Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * Copyright © 2008 Keith Packard
0003  *
0004  * Permission to use, copy, modify, distribute, and sell this software and its
0005  * documentation for any purpose is hereby granted without fee, provided that
0006  * the above copyright notice appear in all copies and that both that copyright
0007  * notice and this permission notice appear in supporting documentation, and
0008  * that the name of the copyright holders not be used in advertising or
0009  * publicity pertaining to distribution of the software without specific,
0010  * written prior permission.  The copyright holders make no representations
0011  * about the suitability of this software for any purpose.  It is provided "as
0012  * is" without express or implied warranty.
0013  *
0014  * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
0015  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
0016  * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
0017  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
0018  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
0019  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
0020  * OF THIS SOFTWARE.
0021  */
0022 
0023 #ifndef _DRM_DP_HELPER_H_
0024 #define _DRM_DP_HELPER_H_
0025 
0026 #include <linux/delay.h>
0027 #include <linux/i2c.h>
0028 
0029 #include <drm/display/drm_dp.h>
0030 #include <drm/drm_connector.h>
0031 
0032 struct drm_device;
0033 struct drm_dp_aux;
0034 struct drm_panel;
0035 
0036 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
0037               int lane_count);
0038 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
0039                   int lane_count);
0040 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
0041                      int lane);
0042 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
0043                       int lane);
0044 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
0045                    int lane);
0046 
0047 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0048                      enum drm_dp_phy dp_phy, bool uhbr);
0049 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0050                  enum drm_dp_phy dp_phy, bool uhbr);
0051 
0052 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
0053                         const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
0054 void drm_dp_lttpr_link_train_clock_recovery_delay(void);
0055 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
0056                     const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
0057 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
0058                           const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
0059 
0060 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux);
0061 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
0062                       int lane_count);
0063 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
0064                     int lane_count);
0065 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
0066 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
0067 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]);
0068 
0069 u8 drm_dp_link_rate_to_bw_code(int link_rate);
0070 int drm_dp_bw_code_to_link_rate(u8 link_bw);
0071 
0072 /**
0073  * struct drm_dp_vsc_sdp - drm DP VSC SDP
0074  *
0075  * This structure represents a DP VSC SDP of drm
0076  * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
0077  * [Table 2-117: VSC SDP Payload for DB16 through DB18]
0078  *
0079  * @sdp_type: secondary-data packet type
0080  * @revision: revision number
0081  * @length: number of valid data bytes
0082  * @pixelformat: pixel encoding format
0083  * @colorimetry: colorimetry format
0084  * @bpc: bit per color
0085  * @dynamic_range: dynamic range information
0086  * @content_type: CTA-861-G defines content types and expected processing by a sink device
0087  */
0088 struct drm_dp_vsc_sdp {
0089     unsigned char sdp_type;
0090     unsigned char revision;
0091     unsigned char length;
0092     enum dp_pixelformat pixelformat;
0093     enum dp_colorimetry colorimetry;
0094     int bpc;
0095     enum dp_dynamic_range dynamic_range;
0096     enum dp_content_type content_type;
0097 };
0098 
0099 void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
0100             const struct drm_dp_vsc_sdp *vsc);
0101 
0102 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
0103 
0104 static inline int
0105 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
0106 {
0107     return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
0108 }
0109 
0110 static inline u8
0111 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
0112 {
0113     return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
0114 }
0115 
0116 static inline bool
0117 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
0118 {
0119     return dpcd[DP_DPCD_REV] >= 0x11 &&
0120         (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
0121 }
0122 
0123 static inline bool
0124 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
0125 {
0126     return dpcd[DP_DPCD_REV] >= 0x11 &&
0127         (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
0128 }
0129 
0130 static inline bool
0131 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
0132 {
0133     return dpcd[DP_DPCD_REV] >= 0x12 &&
0134         dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
0135 }
0136 
0137 static inline bool
0138 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
0139 {
0140     return dpcd[DP_DPCD_REV] >= 0x11 ||
0141         dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5;
0142 }
0143 
0144 static inline bool
0145 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
0146 {
0147     return dpcd[DP_DPCD_REV] >= 0x14 &&
0148         dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
0149 }
0150 
0151 static inline u8
0152 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
0153 {
0154     return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
0155         DP_TRAINING_PATTERN_MASK;
0156 }
0157 
0158 static inline bool
0159 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
0160 {
0161     return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
0162 }
0163 
0164 /* DP/eDP DSC support */
0165 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
0166                    bool is_edp);
0167 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
0168 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
0169                      u8 dsc_bpc[3]);
0170 
0171 static inline bool
0172 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
0173 {
0174     return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
0175         DP_DSC_DECOMPRESSION_IS_SUPPORTED;
0176 }
0177 
0178 static inline u16
0179 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
0180 {
0181     return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
0182         (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
0183          DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
0184          DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
0185 }
0186 
0187 static inline u32
0188 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
0189 {
0190     /* Max Slicewidth = Number of Pixels * 320 */
0191     return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
0192         DP_DSC_SLICE_WIDTH_MULTIPLIER;
0193 }
0194 
0195 /* Forward Error Correction Support on DP 1.4 */
0196 static inline bool
0197 drm_dp_sink_supports_fec(const u8 fec_capable)
0198 {
0199     return fec_capable & DP_FEC_CAPABLE;
0200 }
0201 
0202 static inline bool
0203 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
0204 {
0205     return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
0206 }
0207 
0208 static inline bool
0209 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
0210 {
0211     return dpcd[DP_EDP_CONFIGURATION_CAP] &
0212             DP_ALTERNATE_SCRAMBLER_RESET_CAP;
0213 }
0214 
0215 /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
0216 static inline bool
0217 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
0218 {
0219     return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
0220         DP_MSA_TIMING_PAR_IGNORED;
0221 }
0222 
0223 /**
0224  * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
0225  * @edp_dpcd: The DPCD to check
0226  *
0227  * Note that currently this function will return %false for panels which support various DPCD
0228  * backlight features but which require the brightness be set through PWM, and don't support setting
0229  * the brightness level via the DPCD.
0230  *
0231  * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
0232  * otherwise
0233  */
0234 static inline bool
0235 drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
0236 {
0237     return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP);
0238 }
0239 
0240 /*
0241  * DisplayPort AUX channel
0242  */
0243 
0244 /**
0245  * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
0246  * @address: address of the (first) register to access
0247  * @request: contains the type of transaction (see DP_AUX_* macros)
0248  * @reply: upon completion, contains the reply type of the transaction
0249  * @buffer: pointer to a transmission or reception buffer
0250  * @size: size of @buffer
0251  */
0252 struct drm_dp_aux_msg {
0253     unsigned int address;
0254     u8 request;
0255     u8 reply;
0256     void *buffer;
0257     size_t size;
0258 };
0259 
0260 struct cec_adapter;
0261 struct edid;
0262 struct drm_connector;
0263 
0264 /**
0265  * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
0266  * @lock: mutex protecting this struct
0267  * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
0268  * @connector: the connector this CEC adapter is associated with
0269  * @unregister_work: unregister the CEC adapter
0270  */
0271 struct drm_dp_aux_cec {
0272     struct mutex lock;
0273     struct cec_adapter *adap;
0274     struct drm_connector *connector;
0275     struct delayed_work unregister_work;
0276 };
0277 
0278 /**
0279  * struct drm_dp_aux - DisplayPort AUX channel
0280  *
0281  * An AUX channel can also be used to transport I2C messages to a sink. A
0282  * typical application of that is to access an EDID that's present in the sink
0283  * device. The @transfer() function can also be used to execute such
0284  * transactions. The drm_dp_aux_register() function registers an I2C adapter
0285  * that can be passed to drm_probe_ddc(). Upon removal, drivers should call
0286  * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long
0287  * transfers by default; if a partial response is received, the adapter will
0288  * drop down to the size given by the partial response for this transaction
0289  * only.
0290  */
0291 struct drm_dp_aux {
0292     /**
0293      * @name: user-visible name of this AUX channel and the
0294      * I2C-over-AUX adapter.
0295      *
0296      * It's also used to specify the name of the I2C adapter. If set
0297      * to %NULL, dev_name() of @dev will be used.
0298      */
0299     const char *name;
0300 
0301     /**
0302      * @ddc: I2C adapter that can be used for I2C-over-AUX
0303      * communication
0304      */
0305     struct i2c_adapter ddc;
0306 
0307     /**
0308      * @dev: pointer to struct device that is the parent for this
0309      * AUX channel.
0310      */
0311     struct device *dev;
0312 
0313     /**
0314      * @drm_dev: pointer to the &drm_device that owns this AUX channel.
0315      * Beware, this may be %NULL before drm_dp_aux_register() has been
0316      * called.
0317      *
0318      * It should be set to the &drm_device that will be using this AUX
0319      * channel as early as possible. For many graphics drivers this should
0320      * happen before drm_dp_aux_init(), however it's perfectly fine to set
0321      * this field later so long as it's assigned before calling
0322      * drm_dp_aux_register().
0323      */
0324     struct drm_device *drm_dev;
0325 
0326     /**
0327      * @crtc: backpointer to the crtc that is currently using this
0328      * AUX channel
0329      */
0330     struct drm_crtc *crtc;
0331 
0332     /**
0333      * @hw_mutex: internal mutex used for locking transfers.
0334      *
0335      * Note that if the underlying hardware is shared among multiple
0336      * channels, the driver needs to do additional locking to
0337      * prevent concurrent access.
0338      */
0339     struct mutex hw_mutex;
0340 
0341     /**
0342      * @crc_work: worker that captures CRCs for each frame
0343      */
0344     struct work_struct crc_work;
0345 
0346     /**
0347      * @crc_count: counter of captured frame CRCs
0348      */
0349     u8 crc_count;
0350 
0351     /**
0352      * @transfer: transfers a message representing a single AUX
0353      * transaction.
0354      *
0355      * This is a hardware-specific implementation of how
0356      * transactions are executed that the drivers must provide.
0357      *
0358      * A pointer to a &drm_dp_aux_msg structure describing the
0359      * transaction is passed into this function. Upon success, the
0360      * implementation should return the number of payload bytes that
0361      * were transferred, or a negative error-code on failure.
0362      *
0363      * Helpers will propagate these errors, with the exception of
0364      * the %-EBUSY error, which causes a transaction to be retried.
0365      * On a short, helpers will return %-EPROTO to make it simpler
0366      * to check for failure.
0367      *
0368      * The @transfer() function must only modify the reply field of
0369      * the &drm_dp_aux_msg structure. The retry logic and i2c
0370      * helpers assume this is the case.
0371      *
0372      * Also note that this callback can be called no matter the
0373      * state @dev is in and also no matter what state the panel is
0374      * in. It's expected:
0375      *
0376      * - If the @dev providing the AUX bus is currently unpowered then
0377      *   it will power itself up for the transfer.
0378      *
0379      * - If we're on eDP (using a drm_panel) and the panel is not in a
0380      *   state where it can respond (it's not powered or it's in a
0381      *   low power state) then this function may return an error, but
0382      *   not crash. It's up to the caller of this code to make sure that
0383      *   the panel is powered on if getting an error back is not OK. If a
0384      *   drm_panel driver is initiating a DP AUX transfer it may power
0385      *   itself up however it wants. All other code should ensure that
0386      *   the pre_enable() bridge chain (which eventually calls the
0387      *   drm_panel prepare function) has powered the panel.
0388      */
0389     ssize_t (*transfer)(struct drm_dp_aux *aux,
0390                 struct drm_dp_aux_msg *msg);
0391 
0392     /**
0393      * @wait_hpd_asserted: wait for HPD to be asserted
0394      *
0395      * This is mainly useful for eDP panels drivers to wait for an eDP
0396      * panel to finish powering on. This is an optional function.
0397      *
0398      * This function will efficiently wait for the HPD signal to be
0399      * asserted. The `wait_us` parameter that is passed in says that we
0400      * know that the HPD signal is expected to be asserted within `wait_us`
0401      * microseconds. This function could wait for longer than `wait_us` if
0402      * the logic in the DP controller has a long debouncing time. The
0403      * important thing is that if this function returns success that the
0404      * DP controller is ready to send AUX transactions.
0405      *
0406      * This function returns 0 if HPD was asserted or -ETIMEDOUT if time
0407      * expired and HPD wasn't asserted. This function should not print
0408      * timeout errors to the log.
0409      *
0410      * The semantics of this function are designed to match the
0411      * readx_poll_timeout() function. That means a `wait_us` of 0 means
0412      * to wait forever. Like readx_poll_timeout(), this function may sleep.
0413      *
0414      * NOTE: this function specifically reports the state of the HPD pin
0415      * that's associated with the DP AUX channel. This is different from
0416      * the HPD concept in much of the rest of DRM which is more about
0417      * physical presence of a display. For eDP, for instance, a display is
0418      * assumed always present even if the HPD pin is deasserted.
0419      */
0420     int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us);
0421 
0422     /**
0423      * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
0424      */
0425     unsigned i2c_nack_count;
0426     /**
0427      * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
0428      */
0429     unsigned i2c_defer_count;
0430     /**
0431      * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
0432      */
0433     struct drm_dp_aux_cec cec;
0434     /**
0435      * @is_remote: Is this AUX CH actually using sideband messaging.
0436      */
0437     bool is_remote;
0438 };
0439 
0440 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset);
0441 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
0442              void *buffer, size_t size);
0443 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
0444               void *buffer, size_t size);
0445 
0446 /**
0447  * drm_dp_dpcd_readb() - read a single byte from the DPCD
0448  * @aux: DisplayPort AUX channel
0449  * @offset: address of the register to read
0450  * @valuep: location where the value of the register will be stored
0451  *
0452  * Returns the number of bytes transferred (1) on success, or a negative
0453  * error code on failure.
0454  */
0455 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
0456                     unsigned int offset, u8 *valuep)
0457 {
0458     return drm_dp_dpcd_read(aux, offset, valuep, 1);
0459 }
0460 
0461 /**
0462  * drm_dp_dpcd_writeb() - write a single byte to the DPCD
0463  * @aux: DisplayPort AUX channel
0464  * @offset: address of the register to write
0465  * @value: value to write to the register
0466  *
0467  * Returns the number of bytes transferred (1) on success, or a negative
0468  * error code on failure.
0469  */
0470 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
0471                      unsigned int offset, u8 value)
0472 {
0473     return drm_dp_dpcd_write(aux, offset, &value, 1);
0474 }
0475 
0476 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
0477               u8 dpcd[DP_RECEIVER_CAP_SIZE]);
0478 
0479 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
0480                  u8 status[DP_LINK_STATUS_SIZE]);
0481 
0482 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
0483                      enum drm_dp_phy dp_phy,
0484                      u8 link_status[DP_LINK_STATUS_SIZE]);
0485 
0486 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
0487                     u8 real_edid_checksum);
0488 
0489 int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
0490                 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0491                 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
0492 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0493                    const u8 port_cap[4], u8 type);
0494 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0495                    const u8 port_cap[4],
0496                    const struct edid *edid);
0497 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0498                    const u8 port_cap[4]);
0499 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0500                      const u8 port_cap[4],
0501                      const struct edid *edid);
0502 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0503                      const u8 port_cap[4],
0504                      const struct edid *edid);
0505 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0506                   const u8 port_cap[4],
0507                   const struct edid *edid);
0508 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0509                        const u8 port_cap[4]);
0510 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0511                          const u8 port_cap[4]);
0512 struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
0513                         const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0514                         const u8 port_cap[4]);
0515 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
0516 void drm_dp_downstream_debug(struct seq_file *m,
0517                  const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0518                  const u8 port_cap[4],
0519                  const struct edid *edid,
0520                  struct drm_dp_aux *aux);
0521 enum drm_mode_subconnector
0522 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0523              const u8 port_cap[4]);
0524 void drm_dp_set_subconnector_property(struct drm_connector *connector,
0525                       enum drm_connector_status status,
0526                       const u8 *dpcd,
0527                       const u8 port_cap[4]);
0528 
0529 struct drm_dp_desc;
0530 bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
0531                 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0532                 const struct drm_dp_desc *desc);
0533 int drm_dp_read_sink_count(struct drm_dp_aux *aux);
0534 
0535 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
0536                   const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0537                   u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
0538 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
0539                    const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0540                    enum drm_dp_phy dp_phy,
0541                    u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
0542 int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
0543 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
0544 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
0545 bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
0546 bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
0547 
0548 void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
0549 void drm_dp_aux_init(struct drm_dp_aux *aux);
0550 int drm_dp_aux_register(struct drm_dp_aux *aux);
0551 void drm_dp_aux_unregister(struct drm_dp_aux *aux);
0552 
0553 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
0554 int drm_dp_stop_crc(struct drm_dp_aux *aux);
0555 
0556 struct drm_dp_dpcd_ident {
0557     u8 oui[3];
0558     u8 device_id[6];
0559     u8 hw_rev;
0560     u8 sw_major_rev;
0561     u8 sw_minor_rev;
0562 } __packed;
0563 
0564 /**
0565  * struct drm_dp_desc - DP branch/sink device descriptor
0566  * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
0567  * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
0568  */
0569 struct drm_dp_desc {
0570     struct drm_dp_dpcd_ident ident;
0571     u32 quirks;
0572 };
0573 
0574 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
0575              bool is_branch);
0576 
0577 /**
0578  * enum drm_dp_quirk - Display Port sink/branch device specific quirks
0579  *
0580  * Display Port sink and branch devices in the wild have a variety of bugs, try
0581  * to collect them here. The quirks are shared, but it's up to the drivers to
0582  * implement workarounds for them.
0583  */
0584 enum drm_dp_quirk {
0585     /**
0586      * @DP_DPCD_QUIRK_CONSTANT_N:
0587      *
0588      * The device requires main link attributes Mvid and Nvid to be limited
0589      * to 16 bits. So will give a constant value (0x8000) for compatability.
0590      */
0591     DP_DPCD_QUIRK_CONSTANT_N,
0592     /**
0593      * @DP_DPCD_QUIRK_NO_PSR:
0594      *
0595      * The device does not support PSR even if reports that it supports or
0596      * driver still need to implement proper handling for such device.
0597      */
0598     DP_DPCD_QUIRK_NO_PSR,
0599     /**
0600      * @DP_DPCD_QUIRK_NO_SINK_COUNT:
0601      *
0602      * The device does not set SINK_COUNT to a non-zero value.
0603      * The driver should ignore SINK_COUNT during detection. Note that
0604      * drm_dp_read_sink_count_cap() automatically checks for this quirk.
0605      */
0606     DP_DPCD_QUIRK_NO_SINK_COUNT,
0607     /**
0608      * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
0609      *
0610      * The device supports MST DSC despite not supporting Virtual DPCD.
0611      * The DSC caps can be read from the physical aux instead.
0612      */
0613     DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
0614     /**
0615      * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
0616      *
0617      * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
0618      * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
0619      */
0620     DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
0621 };
0622 
0623 /**
0624  * drm_dp_has_quirk() - does the DP device have a specific quirk
0625  * @desc: Device descriptor filled by drm_dp_read_desc()
0626  * @quirk: Quirk to query for
0627  *
0628  * Return true if DP device identified by @desc has @quirk.
0629  */
0630 static inline bool
0631 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
0632 {
0633     return desc->quirks & BIT(quirk);
0634 }
0635 
0636 /**
0637  * struct drm_edp_backlight_info - Probed eDP backlight info struct
0638  * @pwmgen_bit_count: The pwmgen bit count
0639  * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
0640  * @max: The maximum backlight level that may be set
0641  * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
0642  * @aux_enable: Does the panel support the AUX enable cap?
0643  * @aux_set: Does the panel support setting the brightness through AUX?
0644  *
0645  * This structure contains various data about an eDP backlight, which can be populated by using
0646  * drm_edp_backlight_init().
0647  */
0648 struct drm_edp_backlight_info {
0649     u8 pwmgen_bit_count;
0650     u8 pwm_freq_pre_divider;
0651     u16 max;
0652 
0653     bool lsb_reg_used : 1;
0654     bool aux_enable : 1;
0655     bool aux_set : 1;
0656 };
0657 
0658 int
0659 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
0660                u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
0661                u16 *current_level, u8 *current_mode);
0662 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
0663                 u16 level);
0664 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
0665                  u16 level);
0666 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
0667 
0668 #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
0669     (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)))
0670 
0671 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux);
0672 
0673 #else
0674 
0675 static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel,
0676                          struct drm_dp_aux *aux)
0677 {
0678     return 0;
0679 }
0680 
0681 #endif
0682 
0683 #ifdef CONFIG_DRM_DP_CEC
0684 void drm_dp_cec_irq(struct drm_dp_aux *aux);
0685 void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
0686                    struct drm_connector *connector);
0687 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
0688 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
0689 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
0690 #else
0691 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
0692 {
0693 }
0694 
0695 static inline void
0696 drm_dp_cec_register_connector(struct drm_dp_aux *aux,
0697                   struct drm_connector *connector)
0698 {
0699 }
0700 
0701 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
0702 {
0703 }
0704 
0705 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
0706                        const struct edid *edid)
0707 {
0708 }
0709 
0710 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
0711 {
0712 }
0713 
0714 #endif
0715 
0716 /**
0717  * struct drm_dp_phy_test_params - DP Phy Compliance parameters
0718  * @link_rate: Requested Link rate from DPCD 0x219
0719  * @num_lanes: Number of lanes requested by sing through DPCD 0x220
0720  * @phy_pattern: DP Phy test pattern from DPCD 0x248
0721  * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
0722  * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
0723  * @enhanced_frame_cap: flag for enhanced frame capability.
0724  */
0725 struct drm_dp_phy_test_params {
0726     int link_rate;
0727     u8 num_lanes;
0728     u8 phy_pattern;
0729     u8 hbr2_reset[2];
0730     u8 custom80[10];
0731     bool enhanced_frame_cap;
0732 };
0733 
0734 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
0735                 struct drm_dp_phy_test_params *data);
0736 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
0737                 struct drm_dp_phy_test_params *data, u8 dp_rev);
0738 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0739                    const u8 port_cap[4]);
0740 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
0741 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
0742 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
0743                 u8 frl_mode);
0744 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
0745                 u8 frl_type);
0746 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
0747 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
0748 
0749 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
0750 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
0751 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
0752                        struct drm_connector *connector);
0753 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
0754 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
0755 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
0756 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
0757 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux);
0758 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
0759 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]);
0760 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
0761                            const u8 port_cap[4], u8 color_spc);
0762 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
0763 
0764 #endif /* _DRM_DP_HELPER_H_ */
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!