drm/bridge/mhl.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Defines for Mobile High-Definition Link (MHL) interface
0004  *
0005  * Copyright (C) 2015, Samsung Electronics, Co., Ltd.
0006  * Andrzej Hajda <a.hajda@samsung.com>
0007  *
0008  * Based on MHL driver for Android devices.
0009  * Copyright (C) 2013-2014 Silicon Image, Inc.
0010  */
0011
0012 #ifndef __MHL_H__
0013 #define __MHL_H__
0014
0015 #include <linux/types.h>
0016
0017 /* Device Capabilities Registers */
0018 enum {
0019     MHL_DCAP_DEV_STATE,
0020     MHL_DCAP_MHL_VERSION,
0021     MHL_DCAP_CAT,
0022     MHL_DCAP_ADOPTER_ID_H,
0023     MHL_DCAP_ADOPTER_ID_L,
0024     MHL_DCAP_VID_LINK_MODE,
0025     MHL_DCAP_AUD_LINK_MODE,
0026     MHL_DCAP_VIDEO_TYPE,
0027     MHL_DCAP_LOG_DEV_MAP,
0028     MHL_DCAP_BANDWIDTH,
0029     MHL_DCAP_FEATURE_FLAG,
0030     MHL_DCAP_DEVICE_ID_H,
0031     MHL_DCAP_DEVICE_ID_L,
0032     MHL_DCAP_SCRATCHPAD_SIZE,
0033     MHL_DCAP_INT_STAT_SIZE,
0034     MHL_DCAP_RESERVED,
0035     MHL_DCAP_SIZE
0036 };
0037
0038 #define MHL_DCAP_CAT_SINK           0x01
0039 #define MHL_DCAP_CAT_SOURCE         0x02
0040 #define MHL_DCAP_CAT_POWER          0x10
0041 #define MHL_DCAP_CAT_PLIM(x)            ((x) << 5)
0042
0043 #define MHL_DCAP_VID_LINK_RGB444        0x01
0044 #define MHL_DCAP_VID_LINK_YCBCR444      0x02
0045 #define MHL_DCAP_VID_LINK_YCBCR422      0x04
0046 #define MHL_DCAP_VID_LINK_PPIXEL        0x08
0047 #define MHL_DCAP_VID_LINK_ISLANDS       0x10
0048 #define MHL_DCAP_VID_LINK_VGA           0x20
0049 #define MHL_DCAP_VID_LINK_16BPP         0x40
0050
0051 #define MHL_DCAP_AUD_LINK_2CH           0x01
0052 #define MHL_DCAP_AUD_LINK_8CH           0x02
0053
0054 #define MHL_DCAP_VT_GRAPHICS            0x00
0055 #define MHL_DCAP_VT_PHOTO           0x02
0056 #define MHL_DCAP_VT_CINEMA          0x04
0057 #define MHL_DCAP_VT_GAMES           0x08
0058 #define MHL_DCAP_SUPP_VT            0x80
0059
0060 #define MHL_DCAP_LD_DISPLAY         0x01
0061 #define MHL_DCAP_LD_VIDEO           0x02
0062 #define MHL_DCAP_LD_AUDIO           0x04
0063 #define MHL_DCAP_LD_MEDIA           0x08
0064 #define MHL_DCAP_LD_TUNER           0x10
0065 #define MHL_DCAP_LD_RECORD          0x20
0066 #define MHL_DCAP_LD_SPEAKER         0x40
0067 #define MHL_DCAP_LD_GUI             0x80
0068 #define MHL_DCAP_LD_ALL             0xFF
0069
0070 #define MHL_DCAP_FEATURE_RCP_SUPPORT        0x01
0071 #define MHL_DCAP_FEATURE_RAP_SUPPORT        0x02
0072 #define MHL_DCAP_FEATURE_SP_SUPPORT     0x04
0073 #define MHL_DCAP_FEATURE_UCP_SEND_SUPPOR    0x08
0074 #define MHL_DCAP_FEATURE_UCP_RECV_SUPPORT   0x10
0075 #define MHL_DCAP_FEATURE_RBP_SUPPORT        0x40
0076
0077 /* Extended Device Capabilities Registers */
0078 enum {
0079     MHL_XDC_ECBUS_SPEEDS,
0080     MHL_XDC_TMDS_SPEEDS,
0081     MHL_XDC_ECBUS_ROLES,
0082     MHL_XDC_LOG_DEV_MAPX,
0083     MHL_XDC_SIZE
0084 };
0085
0086 #define MHL_XDC_ECBUS_S_075         0x01
0087 #define MHL_XDC_ECBUS_S_8BIT            0x02
0088 #define MHL_XDC_ECBUS_S_12BIT           0x04
0089 #define MHL_XDC_ECBUS_D_150         0x10
0090 #define MHL_XDC_ECBUS_D_8BIT            0x20
0091
0092 #define MHL_XDC_TMDS_000            0x00
0093 #define MHL_XDC_TMDS_150            0x01
0094 #define MHL_XDC_TMDS_300            0x02
0095 #define MHL_XDC_TMDS_600            0x04
0096
0097 /* MHL_XDC_ECBUS_ROLES flags */
0098 #define MHL_XDC_DEV_HOST            0x01
0099 #define MHL_XDC_DEV_DEVICE          0x02
0100 #define MHL_XDC_DEV_CHARGER         0x04
0101 #define MHL_XDC_HID_HOST            0x08
0102 #define MHL_XDC_HID_DEVICE          0x10
0103
0104 /* MHL_XDC_LOG_DEV_MAPX flags */
0105 #define MHL_XDC_LD_PHONE            0x01
0106
0107 /* Device Status Registers */
0108 enum {
0109     MHL_DST_CONNECTED_RDY,
0110     MHL_DST_LINK_MODE,
0111     MHL_DST_VERSION,
0112     MHL_DST_SIZE
0113 };
0114
0115 /* Offset of DEVSTAT registers */
0116 #define MHL_DST_OFFSET              0x30
0117 #define MHL_DST_REG(name) (MHL_DST_OFFSET + MHL_DST_##name)
0118
0119 #define MHL_DST_CONN_DCAP_RDY           0x01
0120 #define MHL_DST_CONN_XDEVCAPP_SUPP      0x02
0121 #define MHL_DST_CONN_POW_STAT           0x04
0122 #define MHL_DST_CONN_PLIM_STAT_MASK     0x38
0123
0124 #define MHL_DST_LM_CLK_MODE_MASK        0x07
0125 #define MHL_DST_LM_CLK_MODE_PACKED_PIXEL    0x02
0126 #define MHL_DST_LM_CLK_MODE_NORMAL      0x03
0127 #define MHL_DST_LM_PATH_EN_MASK         0x08
0128 #define MHL_DST_LM_PATH_ENABLED         0x08
0129 #define MHL_DST_LM_PATH_DISABLED        0x00
0130 #define MHL_DST_LM_MUTED_MASK           0x10
0131
0132 /* Extended Device Status Registers */
0133 enum {
0134     MHL_XDS_CURR_ECBUS_MODE,
0135     MHL_XDS_AVLINK_MODE_STATUS,
0136     MHL_XDS_AVLINK_MODE_CONTROL,
0137     MHL_XDS_MULTI_SINK_STATUS,
0138     MHL_XDS_SIZE
0139 };
0140
0141 /* Offset of XDEVSTAT registers */
0142 #define MHL_XDS_OFFSET              0x90
0143 #define MHL_XDS_REG(name) (MHL_XDS_OFFSET + MHL_XDS_##name)
0144
0145 /* MHL_XDS_REG_CURR_ECBUS_MODE flags */
0146 #define MHL_XDS_SLOT_MODE_8BIT          0x00
0147 #define MHL_XDS_SLOT_MODE_6BIT          0x01
0148 #define MHL_XDS_ECBUS_S             0x04
0149 #define MHL_XDS_ECBUS_D             0x08
0150
0151 #define MHL_XDS_LINK_CLOCK_75MHZ        0x00
0152 #define MHL_XDS_LINK_CLOCK_150MHZ       0x10
0153 #define MHL_XDS_LINK_CLOCK_300MHZ       0x20
0154 #define MHL_XDS_LINK_CLOCK_600MHZ       0x30
0155
0156 #define MHL_XDS_LINK_STATUS_NO_SIGNAL       0x00
0157 #define MHL_XDS_LINK_STATUS_CRU_LOCKED      0x01
0158 #define MHL_XDS_LINK_STATUS_TMDS_NORMAL     0x02
0159 #define MHL_XDS_LINK_STATUS_TMDS_RESERVED   0x03
0160
0161 #define MHL_XDS_LINK_RATE_1_5_GBPS      0x00
0162 #define MHL_XDS_LINK_RATE_3_0_GBPS      0x01
0163 #define MHL_XDS_LINK_RATE_6_0_GBPS      0x02
0164 #define MHL_XDS_ATT_CAPABLE         0x08
0165
0166 #define MHL_XDS_SINK_STATUS_1_HPD_LOW       0x00
0167 #define MHL_XDS_SINK_STATUS_1_HPD_HIGH      0x01
0168 #define MHL_XDS_SINK_STATUS_2_HPD_LOW       0x00
0169 #define MHL_XDS_SINK_STATUS_2_HPD_HIGH      0x04
0170 #define MHL_XDS_SINK_STATUS_3_HPD_LOW       0x00
0171 #define MHL_XDS_SINK_STATUS_3_HPD_HIGH      0x10
0172 #define MHL_XDS_SINK_STATUS_4_HPD_LOW       0x00
0173 #define MHL_XDS_SINK_STATUS_4_HPD_HIGH      0x40
0174
0175 /* Interrupt Registers */
0176 enum {
0177     MHL_INT_RCHANGE,
0178     MHL_INT_DCHANGE,
0179     MHL_INT_SIZE
0180 };
0181
0182 /* Offset of DEVSTAT registers */
0183 #define MHL_INT_OFFSET              0x20
0184 #define MHL_INT_REG(name) (MHL_INT_OFFSET + MHL_INT_##name)
0185
0186 #define MHL_INT_RC_DCAP_CHG         0x01
0187 #define MHL_INT_RC_DSCR_CHG         0x02
0188 #define MHL_INT_RC_REQ_WRT          0x04
0189 #define MHL_INT_RC_GRT_WRT          0x08
0190 #define MHL_INT_RC_3D_REQ           0x10
0191 #define MHL_INT_RC_FEAT_REQ         0x20
0192 #define MHL_INT_RC_FEAT_COMPLETE        0x40
0193
0194 #define MHL_INT_DC_EDID_CHG         0x02
0195
0196 enum {
0197     MHL_ACK = 0x33, /* Command or Data byte acknowledge */
0198     MHL_NACK = 0x34, /* Command or Data byte not acknowledge */
0199     MHL_ABORT = 0x35, /* Transaction abort */
0200     MHL_WRITE_STAT = 0xe0, /* Write one status register */
0201     MHL_SET_INT = 0x60, /* Write one interrupt register */
0202     MHL_READ_DEVCAP_REG = 0x61, /* Read one register */
0203     MHL_GET_STATE = 0x62, /* Read CBUS revision level from follower */
0204     MHL_GET_VENDOR_ID = 0x63, /* Read vendor ID value from follower */
0205     MHL_SET_HPD = 0x64, /* Set Hot Plug Detect in follower */
0206     MHL_CLR_HPD = 0x65, /* Clear Hot Plug Detect in follower */
0207     MHL_SET_CAP_ID = 0x66, /* Set Capture ID for downstream device */
0208     MHL_GET_CAP_ID = 0x67, /* Get Capture ID from downstream device */
0209     MHL_MSC_MSG = 0x68, /* VS command to send RCP sub-commands */
0210     MHL_GET_SC1_ERRORCODE = 0x69, /* Get Vendor-Specific error code */
0211     MHL_GET_DDC_ERRORCODE = 0x6A, /* Get DDC channel command error code */
0212     MHL_GET_MSC_ERRORCODE = 0x6B, /* Get MSC command error code */
0213     MHL_WRITE_BURST = 0x6C, /* Write 1-16 bytes to responder's scratchpad */
0214     MHL_GET_SC3_ERRORCODE = 0x6D, /* Get channel 3 command error code */
0215     MHL_WRITE_XSTAT = 0x70, /* Write one extended status register */
0216     MHL_READ_XDEVCAP_REG = 0x71, /* Read one extended devcap register */
0217     /* let the rest of these float, they are software specific */
0218     MHL_READ_EDID_BLOCK,
0219     MHL_SEND_3D_REQ_OR_FEAT_REQ,
0220     MHL_READ_DEVCAP,
0221     MHL_READ_XDEVCAP
0222 };
0223
0224 /* MSC message types */
0225 enum {
0226     MHL_MSC_MSG_RCP = 0x10, /* RCP sub-command */
0227     MHL_MSC_MSG_RCPK = 0x11, /* RCP Acknowledge sub-command */
0228     MHL_MSC_MSG_RCPE = 0x12, /* RCP Error sub-command */
0229     MHL_MSC_MSG_RAP = 0x20, /* Mode Change Warning sub-command */
0230     MHL_MSC_MSG_RAPK = 0x21, /* MCW Acknowledge sub-command */
0231     MHL_MSC_MSG_RBP = 0x22, /* Remote Button Protocol sub-command */
0232     MHL_MSC_MSG_RBPK = 0x23, /* RBP Acknowledge sub-command */
0233     MHL_MSC_MSG_RBPE = 0x24, /* RBP Error sub-command */
0234     MHL_MSC_MSG_UCP = 0x30, /* UCP sub-command */
0235     MHL_MSC_MSG_UCPK = 0x31, /* UCP Acknowledge sub-command */
0236     MHL_MSC_MSG_UCPE = 0x32, /* UCP Error sub-command */
0237     MHL_MSC_MSG_RUSB = 0x40, /* Request USB host role */
0238     MHL_MSC_MSG_RUSBK = 0x41, /* Acknowledge request for USB host role */
0239     MHL_MSC_MSG_RHID = 0x42, /* Request HID host role */
0240     MHL_MSC_MSG_RHIDK = 0x43, /* Acknowledge request for HID host role */
0241     MHL_MSC_MSG_ATT = 0x50, /* Request attention sub-command */
0242     MHL_MSC_MSG_ATTK = 0x51, /* ATT Acknowledge sub-command */
0243     MHL_MSC_MSG_BIST_TRIGGER = 0x60,
0244     MHL_MSC_MSG_BIST_REQUEST_STAT = 0x61,
0245     MHL_MSC_MSG_BIST_READY = 0x62,
0246     MHL_MSC_MSG_BIST_STOP = 0x63,
0247 };
0248
0249 /* RAP action codes */
0250 #define MHL_RAP_POLL        0x00    /* Just do an ack */
0251 #define MHL_RAP_CONTENT_ON  0x10    /* Turn content stream ON */
0252 #define MHL_RAP_CONTENT_OFF 0x11    /* Turn content stream OFF */
0253 #define MHL_RAP_CBUS_MODE_DOWN  0x20
0254 #define MHL_RAP_CBUS_MODE_UP    0x21
0255
0256 /* RAPK status codes */
0257 #define MHL_RAPK_NO_ERR     0x00    /* RAP action recognized & supported */
0258 #define MHL_RAPK_UNRECOGNIZED   0x01    /* Unknown RAP action code received */
0259 #define MHL_RAPK_UNSUPPORTED    0x02    /* Rcvd RAP action code not supported */
0260 #define MHL_RAPK_BUSY       0x03    /* Responder too busy to respond */
0261
0262 /* Bit masks for RCP messages */
0263 #define MHL_RCP_KEY_RELEASED_MASK   0x80
0264 #define MHL_RCP_KEY_ID_MASK     0x7F
0265
0266 /*
0267  * Error status codes for RCPE messages
0268  */
0269 /* No error. (Not allowed in RCPE messages) */
0270 #define MHL_RCPE_STATUS_NO_ERROR        0x00
0271 /* Unsupported/unrecognized key code */
0272 #define MHL_RCPE_STATUS_INEFFECTIVE_KEY_CODE    0x01
0273 /* Responder busy. Initiator may retry message */
0274 #define MHL_RCPE_STATUS_BUSY            0x02
0275
0276 /*
0277  * Error status codes for RBPE messages
0278  */
0279 /* No error. (Not allowed in RBPE messages) */
0280 #define MHL_RBPE_STATUS_NO_ERROR        0x00
0281 /* Unsupported/unrecognized button code */
0282 #define MHL_RBPE_STATUS_INEFFECTIVE_BUTTON_CODE 0x01
0283 /* Responder busy. Initiator may retry message */
0284 #define MHL_RBPE_STATUS_BUSY            0x02
0285
0286 /*
0287  * Error status codes for UCPE messages
0288  */
0289 /* No error. (Not allowed in UCPE messages) */
0290 #define MHL_UCPE_STATUS_NO_ERROR        0x00
0291 /* Unsupported/unrecognized key code */
0292 #define MHL_UCPE_STATUS_INEFFECTIVE_KEY_CODE    0x01
0293
0294 enum mhl_burst_id {
0295     MHL_BURST_ID_3D_VIC = 0x10,
0296     MHL_BURST_ID_3D_DTD = 0x11,
0297     MHL_BURST_ID_HEV_VIC = 0x20,
0298     MHL_BURST_ID_HEV_DTDA = 0x21,
0299     MHL_BURST_ID_HEV_DTDB = 0x22,
0300     MHL_BURST_ID_VC_ASSIGN = 0x38,
0301     MHL_BURST_ID_VC_CONFIRM = 0x39,
0302     MHL_BURST_ID_AUD_DELAY = 0x40,
0303     MHL_BURST_ID_ADT_BURSTID = 0x41,
0304     MHL_BURST_ID_BIST_SETUP = 0x51,
0305     MHL_BURST_ID_BIST_RETURN_STAT = 0x52,
0306     MHL_BURST_ID_EMSC_SUPPORT = 0x61,
0307     MHL_BURST_ID_HID_PAYLOAD = 0x62,
0308     MHL_BURST_ID_BLK_RCV_BUFFER_INFO = 0x63,
0309     MHL_BURST_ID_BITS_PER_PIXEL_FMT = 0x64,
0310 };
0311
0312 struct mhl_burst_blk_rcv_buffer_info {
0313     __be16 id;
0314     __le16 size;
0315 } __packed;
0316
0317 struct mhl3_burst_header {
0318     __be16 id;
0319     u8 checksum;
0320     u8 total_entries;
0321     u8 sequence_index;
0322 } __packed;
0323
0324 struct mhl_burst_bits_per_pixel_fmt {
0325     struct mhl3_burst_header hdr;
0326     u8 num_entries;
0327     struct {
0328         u8 stream_id;
0329         u8 pixel_format;
0330     } __packed desc[];
0331 } __packed;
0332
0333 struct mhl_burst_emsc_support {
0334     struct mhl3_burst_header hdr;
0335     u8 num_entries;
0336     __be16 burst_id[];
0337 } __packed;
0338
0339 struct mhl_burst_audio_descr {
0340     struct mhl3_burst_header hdr;
0341     u8 flags;
0342     u8 short_desc[9];
0343 } __packed;
0344
0345 /*
0346  * MHL3 infoframe related definitions
0347  */
0348
0349 #define MHL3_IEEE_OUI       0x7ca61d
0350 #define MHL3_INFOFRAME_SIZE 15
0351
0352 enum mhl3_video_format {
0353     MHL3_VIDEO_FORMAT_NONE,
0354     MHL3_VIDEO_FORMAT_3D,
0355     MHL3_VIDEO_FORMAT_MULTI_VIEW,
0356     MHL3_VIDEO_FORMAT_DUAL_3D
0357 };
0358
0359 enum mhl3_3d_format_type {
0360     MHL3_3D_FORMAT_TYPE_FS, /* frame sequential */
0361     MHL3_3D_FORMAT_TYPE_TB, /* top-bottom */
0362     MHL3_3D_FORMAT_TYPE_LR, /* left-right */
0363     MHL3_3D_FORMAT_TYPE_FS_TB, /* frame sequential, top-bottom */
0364     MHL3_3D_FORMAT_TYPE_FS_LR, /* frame sequential, left-right */
0365     MHL3_3D_FORMAT_TYPE_TB_LR /* top-bottom, left-right */
0366 };
0367
0368 struct mhl3_infoframe {
0369     unsigned char version;
0370     enum mhl3_video_format video_format;
0371     enum mhl3_3d_format_type format_type;
0372     bool sep_audio;
0373     int hev_format;
0374     int av_delay;
0375 };
0376
0377 #endif /* __MHL_H__ */