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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2011 Freescale Semiconductor, Inc.
0004  */
0005 
0006 #ifndef __DW_HDMI__
0007 #define __DW_HDMI__
0008 
0009 #include <sound/hdmi-codec.h>
0010 
0011 struct drm_display_info;
0012 struct drm_display_mode;
0013 struct drm_encoder;
0014 struct dw_hdmi;
0015 struct platform_device;
0016 
0017 /**
0018  * DOC: Supported input formats and encodings
0019  *
0020  * Depending on the Hardware configuration of the Controller IP, it supports
0021  * a subset of the following input formats and encodings on its internal
0022  * 48bit bus.
0023  *
0024  * +----------------------+----------------------------------+------------------------------+
0025  * | Format Name          | Format Code                      | Encodings                    |
0026  * +----------------------+----------------------------------+------------------------------+
0027  * | RGB 4:4:4 8bit       | ``MEDIA_BUS_FMT_RGB888_1X24``    | ``V4L2_YCBCR_ENC_DEFAULT``   |
0028  * +----------------------+----------------------------------+------------------------------+
0029  * | RGB 4:4:4 10bits     | ``MEDIA_BUS_FMT_RGB101010_1X30`` | ``V4L2_YCBCR_ENC_DEFAULT``   |
0030  * +----------------------+----------------------------------+------------------------------+
0031  * | RGB 4:4:4 12bits     | ``MEDIA_BUS_FMT_RGB121212_1X36`` | ``V4L2_YCBCR_ENC_DEFAULT``   |
0032  * +----------------------+----------------------------------+------------------------------+
0033  * | RGB 4:4:4 16bits     | ``MEDIA_BUS_FMT_RGB161616_1X48`` | ``V4L2_YCBCR_ENC_DEFAULT``   |
0034  * +----------------------+----------------------------------+------------------------------+
0035  * | YCbCr 4:4:4 8bit     | ``MEDIA_BUS_FMT_YUV8_1X24``      | ``V4L2_YCBCR_ENC_601``       |
0036  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
0037  * |                      |                                  | or ``V4L2_YCBCR_ENC_XV601``  |
0038  * |                      |                                  | or ``V4L2_YCBCR_ENC_XV709``  |
0039  * +----------------------+----------------------------------+------------------------------+
0040  * | YCbCr 4:4:4 10bits   | ``MEDIA_BUS_FMT_YUV10_1X30``     | ``V4L2_YCBCR_ENC_601``       |
0041  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
0042  * |                      |                                  | or ``V4L2_YCBCR_ENC_XV601``  |
0043  * |                      |                                  | or ``V4L2_YCBCR_ENC_XV709``  |
0044  * +----------------------+----------------------------------+------------------------------+
0045  * | YCbCr 4:4:4 12bits   | ``MEDIA_BUS_FMT_YUV12_1X36``     | ``V4L2_YCBCR_ENC_601``       |
0046  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
0047  * |                      |                                  | or ``V4L2_YCBCR_ENC_XV601``  |
0048  * |                      |                                  | or ``V4L2_YCBCR_ENC_XV709``  |
0049  * +----------------------+----------------------------------+------------------------------+
0050  * | YCbCr 4:4:4 16bits   | ``MEDIA_BUS_FMT_YUV16_1X48``     | ``V4L2_YCBCR_ENC_601``       |
0051  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
0052  * |                      |                                  | or ``V4L2_YCBCR_ENC_XV601``  |
0053  * |                      |                                  | or ``V4L2_YCBCR_ENC_XV709``  |
0054  * +----------------------+----------------------------------+------------------------------+
0055  * | YCbCr 4:2:2 8bit     | ``MEDIA_BUS_FMT_UYVY8_1X16``     | ``V4L2_YCBCR_ENC_601``       |
0056  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
0057  * +----------------------+----------------------------------+------------------------------+
0058  * | YCbCr 4:2:2 10bits   | ``MEDIA_BUS_FMT_UYVY10_1X20``    | ``V4L2_YCBCR_ENC_601``       |
0059  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
0060  * +----------------------+----------------------------------+------------------------------+
0061  * | YCbCr 4:2:2 12bits   | ``MEDIA_BUS_FMT_UYVY12_1X24``    | ``V4L2_YCBCR_ENC_601``       |
0062  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
0063  * +----------------------+----------------------------------+------------------------------+
0064  * | YCbCr 4:2:0 8bit     | ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` | ``V4L2_YCBCR_ENC_601``       |
0065  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
0066  * +----------------------+----------------------------------+------------------------------+
0067  * | YCbCr 4:2:0 10bits   | ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``| ``V4L2_YCBCR_ENC_601``       |
0068  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
0069  * +----------------------+----------------------------------+------------------------------+
0070  * | YCbCr 4:2:0 12bits   | ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``| ``V4L2_YCBCR_ENC_601``       |
0071  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
0072  * +----------------------+----------------------------------+------------------------------+
0073  * | YCbCr 4:2:0 16bits   | ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``| ``V4L2_YCBCR_ENC_601``       |
0074  * |                      |                                  | or ``V4L2_YCBCR_ENC_709``    |
0075  * +----------------------+----------------------------------+------------------------------+
0076  */
0077 
0078 enum {
0079     DW_HDMI_RES_8,
0080     DW_HDMI_RES_10,
0081     DW_HDMI_RES_12,
0082     DW_HDMI_RES_MAX,
0083 };
0084 
0085 enum dw_hdmi_phy_type {
0086     DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00,
0087     DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2,
0088     DW_HDMI_PHY_DWC_MHL_PHY = 0xc2,
0089     DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2,
0090     DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2,
0091     DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3,
0092     DW_HDMI_PHY_VENDOR_PHY = 0xfe,
0093 };
0094 
0095 struct dw_hdmi_mpll_config {
0096     unsigned long mpixelclock;
0097     struct {
0098         u16 cpce;
0099         u16 gmp;
0100     } res[DW_HDMI_RES_MAX];
0101 };
0102 
0103 struct dw_hdmi_curr_ctrl {
0104     unsigned long mpixelclock;
0105     u16 curr[DW_HDMI_RES_MAX];
0106 };
0107 
0108 struct dw_hdmi_phy_config {
0109     unsigned long mpixelclock;
0110     u16 sym_ctr;    /*clock symbol and transmitter control*/
0111     u16 term;       /*transmission termination value*/
0112     u16 vlev_ctr;   /* voltage level control */
0113 };
0114 
0115 struct dw_hdmi_phy_ops {
0116     int (*init)(struct dw_hdmi *hdmi, void *data,
0117             const struct drm_display_info *display,
0118             const struct drm_display_mode *mode);
0119     void (*disable)(struct dw_hdmi *hdmi, void *data);
0120     enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data);
0121     void (*update_hpd)(struct dw_hdmi *hdmi, void *data,
0122                bool force, bool disabled, bool rxsense);
0123     void (*setup_hpd)(struct dw_hdmi *hdmi, void *data);
0124 };
0125 
0126 struct dw_hdmi_plat_data {
0127     struct regmap *regm;
0128 
0129     unsigned int output_port;
0130 
0131     unsigned long input_bus_encoding;
0132     bool use_drm_infoframe;
0133     bool ycbcr_420_allowed;
0134 
0135     /*
0136      * Private data passed to all the .mode_valid() and .configure_phy()
0137      * callback functions.
0138      */
0139     void *priv_data;
0140 
0141     /* Platform-specific mode validation (optional). */
0142     enum drm_mode_status (*mode_valid)(struct dw_hdmi *hdmi, void *data,
0143                        const struct drm_display_info *info,
0144                        const struct drm_display_mode *mode);
0145 
0146     /* Platform-specific audio enable/disable (optional) */
0147     void (*enable_audio)(struct dw_hdmi *hdmi, int channel,
0148                  int width, int rate, int non_pcm);
0149     void (*disable_audio)(struct dw_hdmi *hdmi);
0150 
0151     /* Vendor PHY support */
0152     const struct dw_hdmi_phy_ops *phy_ops;
0153     const char *phy_name;
0154     void *phy_data;
0155     unsigned int phy_force_vendor;
0156 
0157     /* Synopsys PHY support */
0158     const struct dw_hdmi_mpll_config *mpll_cfg;
0159     const struct dw_hdmi_curr_ctrl *cur_ctr;
0160     const struct dw_hdmi_phy_config *phy_config;
0161     int (*configure_phy)(struct dw_hdmi *hdmi, void *data,
0162                  unsigned long mpixelclock);
0163 
0164     unsigned int disable_cec : 1;
0165 };
0166 
0167 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
0168                   const struct dw_hdmi_plat_data *plat_data);
0169 void dw_hdmi_remove(struct dw_hdmi *hdmi);
0170 void dw_hdmi_unbind(struct dw_hdmi *hdmi);
0171 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
0172                  struct drm_encoder *encoder,
0173                  const struct dw_hdmi_plat_data *plat_data);
0174 
0175 void dw_hdmi_resume(struct dw_hdmi *hdmi);
0176 
0177 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
0178 
0179 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
0180                struct device *codec_dev);
0181 void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm);
0182 void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width);
0183 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
0184 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt);
0185 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, u8 *channel_status);
0186 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca);
0187 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);
0188 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
0189 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi,
0190                        const struct drm_display_info *display);
0191 
0192 /* PHY configuration */
0193 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address);
0194 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
0195                unsigned char addr);
0196 
0197 void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi);
0198 
0199 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable);
0200 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable);
0201 void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi);
0202 
0203 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
0204                            void *data);
0205 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
0206                 bool force, bool disabled, bool rxsense);
0207 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data);
0208 
0209 #endif /* __IMX_HDMI_H__ */
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