include/clocksource/arm_arch_timer.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2012 ARM Ltd.
0004  */
0005 #ifndef __CLKSOURCE_ARM_ARCH_TIMER_H
0006 #define __CLKSOURCE_ARM_ARCH_TIMER_H
0007
0008 #include <linux/bitops.h>
0009 #include <linux/timecounter.h>
0010 #include <linux/types.h>
0011
0012 #define ARCH_TIMER_TYPE_CP15        BIT(0)
0013 #define ARCH_TIMER_TYPE_MEM     BIT(1)
0014
0015 #define ARCH_TIMER_CTRL_ENABLE      (1 << 0)
0016 #define ARCH_TIMER_CTRL_IT_MASK     (1 << 1)
0017 #define ARCH_TIMER_CTRL_IT_STAT     (1 << 2)
0018
0019 #define CNTHCTL_EL1PCTEN        (1 << 0)
0020 #define CNTHCTL_EL1PCEN         (1 << 1)
0021 #define CNTHCTL_EVNTEN          (1 << 2)
0022 #define CNTHCTL_EVNTDIR         (1 << 3)
0023 #define CNTHCTL_EVNTI           (0xF << 4)
0024
0025 enum arch_timer_reg {
0026     ARCH_TIMER_REG_CTRL,
0027     ARCH_TIMER_REG_CVAL,
0028 };
0029
0030 enum arch_timer_ppi_nr {
0031     ARCH_TIMER_PHYS_SECURE_PPI,
0032     ARCH_TIMER_PHYS_NONSECURE_PPI,
0033     ARCH_TIMER_VIRT_PPI,
0034     ARCH_TIMER_HYP_PPI,
0035     ARCH_TIMER_HYP_VIRT_PPI,
0036     ARCH_TIMER_MAX_TIMER_PPI
0037 };
0038
0039 enum arch_timer_spi_nr {
0040     ARCH_TIMER_PHYS_SPI,
0041     ARCH_TIMER_VIRT_SPI,
0042     ARCH_TIMER_MAX_TIMER_SPI
0043 };
0044
0045 #define ARCH_TIMER_PHYS_ACCESS      0
0046 #define ARCH_TIMER_VIRT_ACCESS      1
0047 #define ARCH_TIMER_MEM_PHYS_ACCESS  2
0048 #define ARCH_TIMER_MEM_VIRT_ACCESS  3
0049
0050 #define ARCH_TIMER_MEM_MAX_FRAMES   8
0051
0052 #define ARCH_TIMER_USR_PCT_ACCESS_EN    (1 << 0) /* physical counter */
0053 #define ARCH_TIMER_USR_VCT_ACCESS_EN    (1 << 1) /* virtual counter */
0054 #define ARCH_TIMER_VIRT_EVT_EN      (1 << 2)
0055 #define ARCH_TIMER_EVT_TRIGGER_SHIFT    (4)
0056 #define ARCH_TIMER_EVT_TRIGGER_MASK (0xF << ARCH_TIMER_EVT_TRIGGER_SHIFT)
0057 #define ARCH_TIMER_USR_VT_ACCESS_EN (1 << 8) /* virtual timer registers */
0058 #define ARCH_TIMER_USR_PT_ACCESS_EN (1 << 9) /* physical timer registers */
0059 #define ARCH_TIMER_EVT_INTERVAL_SCALE   (1 << 17) /* EVNTIS in the ARMv8 ARM */
0060
0061 #define ARCH_TIMER_EVT_STREAM_PERIOD_US 100
0062 #define ARCH_TIMER_EVT_STREAM_FREQ              \
0063     (USEC_PER_SEC / ARCH_TIMER_EVT_STREAM_PERIOD_US)
0064
0065 struct arch_timer_kvm_info {
0066     struct timecounter timecounter;
0067     int virtual_irq;
0068     int physical_irq;
0069 };
0070
0071 struct arch_timer_mem_frame {
0072     bool valid;
0073     phys_addr_t cntbase;
0074     size_t size;
0075     int phys_irq;
0076     int virt_irq;
0077 };
0078
0079 struct arch_timer_mem {
0080     phys_addr_t cntctlbase;
0081     size_t size;
0082     struct arch_timer_mem_frame frame[ARCH_TIMER_MEM_MAX_FRAMES];
0083 };
0084
0085 #ifdef CONFIG_ARM_ARCH_TIMER
0086
0087 extern u32 arch_timer_get_rate(void);
0088 extern u64 (*arch_timer_read_counter)(void);
0089 extern struct arch_timer_kvm_info *arch_timer_get_kvm_info(void);
0090 extern bool arch_timer_evtstrm_available(void);
0091
0092 #else
0093
0094 static inline u32 arch_timer_get_rate(void)
0095 {
0096     return 0;
0097 }
0098
0099 static inline u64 arch_timer_read_counter(void)
0100 {
0101     return 0;
0102 }
0103
0104 static inline bool arch_timer_evtstrm_available(void)
0105 {
0106     return false;
0107 }
0108
0109 #endif
0110
0111 #endif