include/asm-generic/iomap.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __GENERIC_IO_H
0003 #define __GENERIC_IO_H
0004
0005 #include <linux/linkage.h>
0006 #include <asm/byteorder.h>
0007
0008 /*
0009  * These are the "generic" interfaces for doing new-style
0010  * memory-mapped or PIO accesses. Architectures may do
0011  * their own arch-optimized versions, these just act as
0012  * wrappers around the old-style IO register access functions:
0013  * read[bwl]/write[bwl]/in[bwl]/out[bwl]
0014  *
0015  * Don't include this directly, include it from <asm/io.h>.
0016  */
0017
0018 /*
0019  * Read/write from/to an (offsettable) iomem cookie. It might be a PIO
0020  * access or a MMIO access, these functions don't care. The info is
0021  * encoded in the hardware mapping set up by the mapping functions
0022  * (or the cookie itself, depending on implementation and hw).
0023  *
0024  * The generic routines just encode the PIO/MMIO as part of the
0025  * cookie, and coldly assume that the MMIO IO mappings are not
0026  * in the low address range. Architectures for which this is not
0027  * true can't use this generic implementation.
0028  */
0029 extern unsigned int ioread8(const void __iomem *);
0030 extern unsigned int ioread16(const void __iomem *);
0031 extern unsigned int ioread16be(const void __iomem *);
0032 extern unsigned int ioread32(const void __iomem *);
0033 extern unsigned int ioread32be(const void __iomem *);
0034 #ifdef CONFIG_64BIT
0035 extern u64 ioread64(const void __iomem *);
0036 extern u64 ioread64be(const void __iomem *);
0037 #endif
0038
0039 #ifdef readq
0040 #define ioread64_lo_hi ioread64_lo_hi
0041 #define ioread64_hi_lo ioread64_hi_lo
0042 #define ioread64be_lo_hi ioread64be_lo_hi
0043 #define ioread64be_hi_lo ioread64be_hi_lo
0044 extern u64 ioread64_lo_hi(const void __iomem *addr);
0045 extern u64 ioread64_hi_lo(const void __iomem *addr);
0046 extern u64 ioread64be_lo_hi(const void __iomem *addr);
0047 extern u64 ioread64be_hi_lo(const void __iomem *addr);
0048 #endif
0049
0050 extern void iowrite8(u8, void __iomem *);
0051 extern void iowrite16(u16, void __iomem *);
0052 extern void iowrite16be(u16, void __iomem *);
0053 extern void iowrite32(u32, void __iomem *);
0054 extern void iowrite32be(u32, void __iomem *);
0055 #ifdef CONFIG_64BIT
0056 extern void iowrite64(u64, void __iomem *);
0057 extern void iowrite64be(u64, void __iomem *);
0058 #endif
0059
0060 #ifdef writeq
0061 #define iowrite64_lo_hi iowrite64_lo_hi
0062 #define iowrite64_hi_lo iowrite64_hi_lo
0063 #define iowrite64be_lo_hi iowrite64be_lo_hi
0064 #define iowrite64be_hi_lo iowrite64be_hi_lo
0065 extern void iowrite64_lo_hi(u64 val, void __iomem *addr);
0066 extern void iowrite64_hi_lo(u64 val, void __iomem *addr);
0067 extern void iowrite64be_lo_hi(u64 val, void __iomem *addr);
0068 extern void iowrite64be_hi_lo(u64 val, void __iomem *addr);
0069 #endif
0070
0071 /*
0072  * "string" versions of the above. Note that they
0073  * use native byte ordering for the accesses (on
0074  * the assumption that IO and memory agree on a
0075  * byte order, and CPU byteorder is irrelevant).
0076  *
0077  * They do _not_ update the port address. If you
0078  * want MMIO that copies stuff laid out in MMIO
0079  * memory across multiple ports, use "memcpy_toio()"
0080  * and friends.
0081  */
0082 extern void ioread8_rep(const void __iomem *port, void *buf, unsigned long count);
0083 extern void ioread16_rep(const void __iomem *port, void *buf, unsigned long count);
0084 extern void ioread32_rep(const void __iomem *port, void *buf, unsigned long count);
0085
0086 extern void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count);
0087 extern void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count);
0088 extern void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count);
0089
0090 #ifdef CONFIG_HAS_IOPORT_MAP
0091 /* Create a virtual mapping cookie for an IO port range */
0092 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
0093 extern void ioport_unmap(void __iomem *);
0094 #endif
0095
0096 #ifndef ARCH_HAS_IOREMAP_WC
0097 #define ioremap_wc ioremap
0098 #endif
0099
0100 #ifndef ARCH_HAS_IOREMAP_WT
0101 #define ioremap_wt ioremap
0102 #endif
0103
0104 #ifndef ARCH_HAS_IOREMAP_NP
0105 /* See the comment in asm-generic/io.h about ioremap_np(). */
0106 #define ioremap_np ioremap_np
0107 static inline void __iomem *ioremap_np(phys_addr_t offset, size_t size)
0108 {
0109     return NULL;
0110 }
0111 #endif
0112
0113 #include <asm-generic/pci_iomap.h>
0114
0115 #endif