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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* Generic I/O port emulation.
0003  *
0004  * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
0005  * Written by David Howells (dhowells@redhat.com)
0006  */
0007 #ifndef __ASM_GENERIC_IO_H
0008 #define __ASM_GENERIC_IO_H
0009 
0010 #include <asm/page.h> /* I/O is all done through memory accesses */
0011 #include <linux/string.h> /* for memset() and memcpy() */
0012 #include <linux/types.h>
0013 #include <linux/instruction_pointer.h>
0014 
0015 #ifdef CONFIG_GENERIC_IOMAP
0016 #include <asm-generic/iomap.h>
0017 #endif
0018 
0019 #include <asm/mmiowb.h>
0020 #include <asm-generic/pci_iomap.h>
0021 
0022 #ifndef __io_br
0023 #define __io_br()      barrier()
0024 #endif
0025 
0026 /* prevent prefetching of coherent DMA data ahead of a dma-complete */
0027 #ifndef __io_ar
0028 #ifdef rmb
0029 #define __io_ar(v)      rmb()
0030 #else
0031 #define __io_ar(v)      barrier()
0032 #endif
0033 #endif
0034 
0035 /* flush writes to coherent DMA data before possibly triggering a DMA read */
0036 #ifndef __io_bw
0037 #ifdef wmb
0038 #define __io_bw()      wmb()
0039 #else
0040 #define __io_bw()      barrier()
0041 #endif
0042 #endif
0043 
0044 /* serialize device access against a spin_unlock, usually handled there. */
0045 #ifndef __io_aw
0046 #define __io_aw()      mmiowb_set_pending()
0047 #endif
0048 
0049 #ifndef __io_pbw
0050 #define __io_pbw()     __io_bw()
0051 #endif
0052 
0053 #ifndef __io_paw
0054 #define __io_paw()     __io_aw()
0055 #endif
0056 
0057 #ifndef __io_pbr
0058 #define __io_pbr()     __io_br()
0059 #endif
0060 
0061 #ifndef __io_par
0062 #define __io_par(v)     __io_ar(v)
0063 #endif
0064 
0065 /*
0066  * "__DISABLE_TRACE_MMIO__" flag can be used to disable MMIO tracing for
0067  * specific kernel drivers in case of excessive/unwanted logging.
0068  *
0069  * Usage: Add a #define flag at the beginning of the driver file.
0070  * Ex: #define __DISABLE_TRACE_MMIO__
0071  *     #include <...>
0072  *     ...
0073  */
0074 #if IS_ENABLED(CONFIG_TRACE_MMIO_ACCESS) && !(defined(__DISABLE_TRACE_MMIO__))
0075 #include <linux/tracepoint-defs.h>
0076 
0077 DECLARE_TRACEPOINT(rwmmio_write);
0078 DECLARE_TRACEPOINT(rwmmio_post_write);
0079 DECLARE_TRACEPOINT(rwmmio_read);
0080 DECLARE_TRACEPOINT(rwmmio_post_read);
0081 
0082 void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
0083             unsigned long caller_addr);
0084 void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
0085              unsigned long caller_addr);
0086 void log_read_mmio(u8 width, const volatile void __iomem *addr,
0087            unsigned long caller_addr);
0088 void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
0089             unsigned long caller_addr);
0090 
0091 #else
0092 
0093 static inline void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
0094                   unsigned long caller_addr) {}
0095 static inline void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
0096                        unsigned long caller_addr) {}
0097 static inline void log_read_mmio(u8 width, const volatile void __iomem *addr,
0098                  unsigned long caller_addr) {}
0099 static inline void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
0100                       unsigned long caller_addr) {}
0101 
0102 #endif /* CONFIG_TRACE_MMIO_ACCESS */
0103 
0104 /*
0105  * __raw_{read,write}{b,w,l,q}() access memory in native endianness.
0106  *
0107  * On some architectures memory mapped IO needs to be accessed differently.
0108  * On the simple architectures, we just read/write the memory location
0109  * directly.
0110  */
0111 
0112 #ifndef __raw_readb
0113 #define __raw_readb __raw_readb
0114 static inline u8 __raw_readb(const volatile void __iomem *addr)
0115 {
0116     return *(const volatile u8 __force *)addr;
0117 }
0118 #endif
0119 
0120 #ifndef __raw_readw
0121 #define __raw_readw __raw_readw
0122 static inline u16 __raw_readw(const volatile void __iomem *addr)
0123 {
0124     return *(const volatile u16 __force *)addr;
0125 }
0126 #endif
0127 
0128 #ifndef __raw_readl
0129 #define __raw_readl __raw_readl
0130 static inline u32 __raw_readl(const volatile void __iomem *addr)
0131 {
0132     return *(const volatile u32 __force *)addr;
0133 }
0134 #endif
0135 
0136 #ifdef CONFIG_64BIT
0137 #ifndef __raw_readq
0138 #define __raw_readq __raw_readq
0139 static inline u64 __raw_readq(const volatile void __iomem *addr)
0140 {
0141     return *(const volatile u64 __force *)addr;
0142 }
0143 #endif
0144 #endif /* CONFIG_64BIT */
0145 
0146 #ifndef __raw_writeb
0147 #define __raw_writeb __raw_writeb
0148 static inline void __raw_writeb(u8 value, volatile void __iomem *addr)
0149 {
0150     *(volatile u8 __force *)addr = value;
0151 }
0152 #endif
0153 
0154 #ifndef __raw_writew
0155 #define __raw_writew __raw_writew
0156 static inline void __raw_writew(u16 value, volatile void __iomem *addr)
0157 {
0158     *(volatile u16 __force *)addr = value;
0159 }
0160 #endif
0161 
0162 #ifndef __raw_writel
0163 #define __raw_writel __raw_writel
0164 static inline void __raw_writel(u32 value, volatile void __iomem *addr)
0165 {
0166     *(volatile u32 __force *)addr = value;
0167 }
0168 #endif
0169 
0170 #ifdef CONFIG_64BIT
0171 #ifndef __raw_writeq
0172 #define __raw_writeq __raw_writeq
0173 static inline void __raw_writeq(u64 value, volatile void __iomem *addr)
0174 {
0175     *(volatile u64 __force *)addr = value;
0176 }
0177 #endif
0178 #endif /* CONFIG_64BIT */
0179 
0180 /*
0181  * {read,write}{b,w,l,q}() access little endian memory and return result in
0182  * native endianness.
0183  */
0184 
0185 #ifndef readb
0186 #define readb readb
0187 static inline u8 readb(const volatile void __iomem *addr)
0188 {
0189     u8 val;
0190 
0191     log_read_mmio(8, addr, _THIS_IP_);
0192     __io_br();
0193     val = __raw_readb(addr);
0194     __io_ar(val);
0195     log_post_read_mmio(val, 8, addr, _THIS_IP_);
0196     return val;
0197 }
0198 #endif
0199 
0200 #ifndef readw
0201 #define readw readw
0202 static inline u16 readw(const volatile void __iomem *addr)
0203 {
0204     u16 val;
0205 
0206     log_read_mmio(16, addr, _THIS_IP_);
0207     __io_br();
0208     val = __le16_to_cpu((__le16 __force)__raw_readw(addr));
0209     __io_ar(val);
0210     log_post_read_mmio(val, 16, addr, _THIS_IP_);
0211     return val;
0212 }
0213 #endif
0214 
0215 #ifndef readl
0216 #define readl readl
0217 static inline u32 readl(const volatile void __iomem *addr)
0218 {
0219     u32 val;
0220 
0221     log_read_mmio(32, addr, _THIS_IP_);
0222     __io_br();
0223     val = __le32_to_cpu((__le32 __force)__raw_readl(addr));
0224     __io_ar(val);
0225     log_post_read_mmio(val, 32, addr, _THIS_IP_);
0226     return val;
0227 }
0228 #endif
0229 
0230 #ifdef CONFIG_64BIT
0231 #ifndef readq
0232 #define readq readq
0233 static inline u64 readq(const volatile void __iomem *addr)
0234 {
0235     u64 val;
0236 
0237     log_read_mmio(64, addr, _THIS_IP_);
0238     __io_br();
0239     val = __le64_to_cpu(__raw_readq(addr));
0240     __io_ar(val);
0241     log_post_read_mmio(val, 64, addr, _THIS_IP_);
0242     return val;
0243 }
0244 #endif
0245 #endif /* CONFIG_64BIT */
0246 
0247 #ifndef writeb
0248 #define writeb writeb
0249 static inline void writeb(u8 value, volatile void __iomem *addr)
0250 {
0251     log_write_mmio(value, 8, addr, _THIS_IP_);
0252     __io_bw();
0253     __raw_writeb(value, addr);
0254     __io_aw();
0255     log_post_write_mmio(value, 8, addr, _THIS_IP_);
0256 }
0257 #endif
0258 
0259 #ifndef writew
0260 #define writew writew
0261 static inline void writew(u16 value, volatile void __iomem *addr)
0262 {
0263     log_write_mmio(value, 16, addr, _THIS_IP_);
0264     __io_bw();
0265     __raw_writew((u16 __force)cpu_to_le16(value), addr);
0266     __io_aw();
0267     log_post_write_mmio(value, 16, addr, _THIS_IP_);
0268 }
0269 #endif
0270 
0271 #ifndef writel
0272 #define writel writel
0273 static inline void writel(u32 value, volatile void __iomem *addr)
0274 {
0275     log_write_mmio(value, 32, addr, _THIS_IP_);
0276     __io_bw();
0277     __raw_writel((u32 __force)__cpu_to_le32(value), addr);
0278     __io_aw();
0279     log_post_write_mmio(value, 32, addr, _THIS_IP_);
0280 }
0281 #endif
0282 
0283 #ifdef CONFIG_64BIT
0284 #ifndef writeq
0285 #define writeq writeq
0286 static inline void writeq(u64 value, volatile void __iomem *addr)
0287 {
0288     log_write_mmio(value, 64, addr, _THIS_IP_);
0289     __io_bw();
0290     __raw_writeq(__cpu_to_le64(value), addr);
0291     __io_aw();
0292     log_post_write_mmio(value, 64, addr, _THIS_IP_);
0293 }
0294 #endif
0295 #endif /* CONFIG_64BIT */
0296 
0297 /*
0298  * {read,write}{b,w,l,q}_relaxed() are like the regular version, but
0299  * are not guaranteed to provide ordering against spinlocks or memory
0300  * accesses.
0301  */
0302 #ifndef readb_relaxed
0303 #define readb_relaxed readb_relaxed
0304 static inline u8 readb_relaxed(const volatile void __iomem *addr)
0305 {
0306     u8 val;
0307 
0308     log_read_mmio(8, addr, _THIS_IP_);
0309     val = __raw_readb(addr);
0310     log_post_read_mmio(val, 8, addr, _THIS_IP_);
0311     return val;
0312 }
0313 #endif
0314 
0315 #ifndef readw_relaxed
0316 #define readw_relaxed readw_relaxed
0317 static inline u16 readw_relaxed(const volatile void __iomem *addr)
0318 {
0319     u16 val;
0320 
0321     log_read_mmio(16, addr, _THIS_IP_);
0322     val = __le16_to_cpu(__raw_readw(addr));
0323     log_post_read_mmio(val, 16, addr, _THIS_IP_);
0324     return val;
0325 }
0326 #endif
0327 
0328 #ifndef readl_relaxed
0329 #define readl_relaxed readl_relaxed
0330 static inline u32 readl_relaxed(const volatile void __iomem *addr)
0331 {
0332     u32 val;
0333 
0334     log_read_mmio(32, addr, _THIS_IP_);
0335     val = __le32_to_cpu(__raw_readl(addr));
0336     log_post_read_mmio(val, 32, addr, _THIS_IP_);
0337     return val;
0338 }
0339 #endif
0340 
0341 #if defined(readq) && !defined(readq_relaxed)
0342 #define readq_relaxed readq_relaxed
0343 static inline u64 readq_relaxed(const volatile void __iomem *addr)
0344 {
0345     u64 val;
0346 
0347     log_read_mmio(64, addr, _THIS_IP_);
0348     val = __le64_to_cpu(__raw_readq(addr));
0349     log_post_read_mmio(val, 64, addr, _THIS_IP_);
0350     return val;
0351 }
0352 #endif
0353 
0354 #ifndef writeb_relaxed
0355 #define writeb_relaxed writeb_relaxed
0356 static inline void writeb_relaxed(u8 value, volatile void __iomem *addr)
0357 {
0358     log_write_mmio(value, 8, addr, _THIS_IP_);
0359     __raw_writeb(value, addr);
0360     log_post_write_mmio(value, 8, addr, _THIS_IP_);
0361 }
0362 #endif
0363 
0364 #ifndef writew_relaxed
0365 #define writew_relaxed writew_relaxed
0366 static inline void writew_relaxed(u16 value, volatile void __iomem *addr)
0367 {
0368     log_write_mmio(value, 16, addr, _THIS_IP_);
0369     __raw_writew(cpu_to_le16(value), addr);
0370     log_post_write_mmio(value, 16, addr, _THIS_IP_);
0371 }
0372 #endif
0373 
0374 #ifndef writel_relaxed
0375 #define writel_relaxed writel_relaxed
0376 static inline void writel_relaxed(u32 value, volatile void __iomem *addr)
0377 {
0378     log_write_mmio(value, 32, addr, _THIS_IP_);
0379     __raw_writel(__cpu_to_le32(value), addr);
0380     log_post_write_mmio(value, 32, addr, _THIS_IP_);
0381 }
0382 #endif
0383 
0384 #if defined(writeq) && !defined(writeq_relaxed)
0385 #define writeq_relaxed writeq_relaxed
0386 static inline void writeq_relaxed(u64 value, volatile void __iomem *addr)
0387 {
0388     log_write_mmio(value, 64, addr, _THIS_IP_);
0389     __raw_writeq(__cpu_to_le64(value), addr);
0390     log_post_write_mmio(value, 64, addr, _THIS_IP_);
0391 }
0392 #endif
0393 
0394 /*
0395  * {read,write}s{b,w,l,q}() repeatedly access the same memory address in
0396  * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times).
0397  */
0398 #ifndef readsb
0399 #define readsb readsb
0400 static inline void readsb(const volatile void __iomem *addr, void *buffer,
0401               unsigned int count)
0402 {
0403     if (count) {
0404         u8 *buf = buffer;
0405 
0406         do {
0407             u8 x = __raw_readb(addr);
0408             *buf++ = x;
0409         } while (--count);
0410     }
0411 }
0412 #endif
0413 
0414 #ifndef readsw
0415 #define readsw readsw
0416 static inline void readsw(const volatile void __iomem *addr, void *buffer,
0417               unsigned int count)
0418 {
0419     if (count) {
0420         u16 *buf = buffer;
0421 
0422         do {
0423             u16 x = __raw_readw(addr);
0424             *buf++ = x;
0425         } while (--count);
0426     }
0427 }
0428 #endif
0429 
0430 #ifndef readsl
0431 #define readsl readsl
0432 static inline void readsl(const volatile void __iomem *addr, void *buffer,
0433               unsigned int count)
0434 {
0435     if (count) {
0436         u32 *buf = buffer;
0437 
0438         do {
0439             u32 x = __raw_readl(addr);
0440             *buf++ = x;
0441         } while (--count);
0442     }
0443 }
0444 #endif
0445 
0446 #ifdef CONFIG_64BIT
0447 #ifndef readsq
0448 #define readsq readsq
0449 static inline void readsq(const volatile void __iomem *addr, void *buffer,
0450               unsigned int count)
0451 {
0452     if (count) {
0453         u64 *buf = buffer;
0454 
0455         do {
0456             u64 x = __raw_readq(addr);
0457             *buf++ = x;
0458         } while (--count);
0459     }
0460 }
0461 #endif
0462 #endif /* CONFIG_64BIT */
0463 
0464 #ifndef writesb
0465 #define writesb writesb
0466 static inline void writesb(volatile void __iomem *addr, const void *buffer,
0467                unsigned int count)
0468 {
0469     if (count) {
0470         const u8 *buf = buffer;
0471 
0472         do {
0473             __raw_writeb(*buf++, addr);
0474         } while (--count);
0475     }
0476 }
0477 #endif
0478 
0479 #ifndef writesw
0480 #define writesw writesw
0481 static inline void writesw(volatile void __iomem *addr, const void *buffer,
0482                unsigned int count)
0483 {
0484     if (count) {
0485         const u16 *buf = buffer;
0486 
0487         do {
0488             __raw_writew(*buf++, addr);
0489         } while (--count);
0490     }
0491 }
0492 #endif
0493 
0494 #ifndef writesl
0495 #define writesl writesl
0496 static inline void writesl(volatile void __iomem *addr, const void *buffer,
0497                unsigned int count)
0498 {
0499     if (count) {
0500         const u32 *buf = buffer;
0501 
0502         do {
0503             __raw_writel(*buf++, addr);
0504         } while (--count);
0505     }
0506 }
0507 #endif
0508 
0509 #ifdef CONFIG_64BIT
0510 #ifndef writesq
0511 #define writesq writesq
0512 static inline void writesq(volatile void __iomem *addr, const void *buffer,
0513                unsigned int count)
0514 {
0515     if (count) {
0516         const u64 *buf = buffer;
0517 
0518         do {
0519             __raw_writeq(*buf++, addr);
0520         } while (--count);
0521     }
0522 }
0523 #endif
0524 #endif /* CONFIG_64BIT */
0525 
0526 #ifndef PCI_IOBASE
0527 #define PCI_IOBASE ((void __iomem *)0)
0528 #endif
0529 
0530 #ifndef IO_SPACE_LIMIT
0531 #define IO_SPACE_LIMIT 0xffff
0532 #endif
0533 
0534 /*
0535  * {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be
0536  * implemented on hardware that needs an additional delay for I/O accesses to
0537  * take effect.
0538  */
0539 
0540 #if !defined(inb) && !defined(_inb)
0541 #define _inb _inb
0542 static inline u8 _inb(unsigned long addr)
0543 {
0544     u8 val;
0545 
0546     __io_pbr();
0547     val = __raw_readb(PCI_IOBASE + addr);
0548     __io_par(val);
0549     return val;
0550 }
0551 #endif
0552 
0553 #if !defined(inw) && !defined(_inw)
0554 #define _inw _inw
0555 static inline u16 _inw(unsigned long addr)
0556 {
0557     u16 val;
0558 
0559     __io_pbr();
0560     val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));
0561     __io_par(val);
0562     return val;
0563 }
0564 #endif
0565 
0566 #if !defined(inl) && !defined(_inl)
0567 #define _inl _inl
0568 static inline u32 _inl(unsigned long addr)
0569 {
0570     u32 val;
0571 
0572     __io_pbr();
0573     val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr));
0574     __io_par(val);
0575     return val;
0576 }
0577 #endif
0578 
0579 #if !defined(outb) && !defined(_outb)
0580 #define _outb _outb
0581 static inline void _outb(u8 value, unsigned long addr)
0582 {
0583     __io_pbw();
0584     __raw_writeb(value, PCI_IOBASE + addr);
0585     __io_paw();
0586 }
0587 #endif
0588 
0589 #if !defined(outw) && !defined(_outw)
0590 #define _outw _outw
0591 static inline void _outw(u16 value, unsigned long addr)
0592 {
0593     __io_pbw();
0594     __raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr);
0595     __io_paw();
0596 }
0597 #endif
0598 
0599 #if !defined(outl) && !defined(_outl)
0600 #define _outl _outl
0601 static inline void _outl(u32 value, unsigned long addr)
0602 {
0603     __io_pbw();
0604     __raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr);
0605     __io_paw();
0606 }
0607 #endif
0608 
0609 #include <linux/logic_pio.h>
0610 
0611 #ifndef inb
0612 #define inb _inb
0613 #endif
0614 
0615 #ifndef inw
0616 #define inw _inw
0617 #endif
0618 
0619 #ifndef inl
0620 #define inl _inl
0621 #endif
0622 
0623 #ifndef outb
0624 #define outb _outb
0625 #endif
0626 
0627 #ifndef outw
0628 #define outw _outw
0629 #endif
0630 
0631 #ifndef outl
0632 #define outl _outl
0633 #endif
0634 
0635 #ifndef inb_p
0636 #define inb_p inb_p
0637 static inline u8 inb_p(unsigned long addr)
0638 {
0639     return inb(addr);
0640 }
0641 #endif
0642 
0643 #ifndef inw_p
0644 #define inw_p inw_p
0645 static inline u16 inw_p(unsigned long addr)
0646 {
0647     return inw(addr);
0648 }
0649 #endif
0650 
0651 #ifndef inl_p
0652 #define inl_p inl_p
0653 static inline u32 inl_p(unsigned long addr)
0654 {
0655     return inl(addr);
0656 }
0657 #endif
0658 
0659 #ifndef outb_p
0660 #define outb_p outb_p
0661 static inline void outb_p(u8 value, unsigned long addr)
0662 {
0663     outb(value, addr);
0664 }
0665 #endif
0666 
0667 #ifndef outw_p
0668 #define outw_p outw_p
0669 static inline void outw_p(u16 value, unsigned long addr)
0670 {
0671     outw(value, addr);
0672 }
0673 #endif
0674 
0675 #ifndef outl_p
0676 #define outl_p outl_p
0677 static inline void outl_p(u32 value, unsigned long addr)
0678 {
0679     outl(value, addr);
0680 }
0681 #endif
0682 
0683 /*
0684  * {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a
0685  * single I/O port multiple times.
0686  */
0687 
0688 #ifndef insb
0689 #define insb insb
0690 static inline void insb(unsigned long addr, void *buffer, unsigned int count)
0691 {
0692     readsb(PCI_IOBASE + addr, buffer, count);
0693 }
0694 #endif
0695 
0696 #ifndef insw
0697 #define insw insw
0698 static inline void insw(unsigned long addr, void *buffer, unsigned int count)
0699 {
0700     readsw(PCI_IOBASE + addr, buffer, count);
0701 }
0702 #endif
0703 
0704 #ifndef insl
0705 #define insl insl
0706 static inline void insl(unsigned long addr, void *buffer, unsigned int count)
0707 {
0708     readsl(PCI_IOBASE + addr, buffer, count);
0709 }
0710 #endif
0711 
0712 #ifndef outsb
0713 #define outsb outsb
0714 static inline void outsb(unsigned long addr, const void *buffer,
0715              unsigned int count)
0716 {
0717     writesb(PCI_IOBASE + addr, buffer, count);
0718 }
0719 #endif
0720 
0721 #ifndef outsw
0722 #define outsw outsw
0723 static inline void outsw(unsigned long addr, const void *buffer,
0724              unsigned int count)
0725 {
0726     writesw(PCI_IOBASE + addr, buffer, count);
0727 }
0728 #endif
0729 
0730 #ifndef outsl
0731 #define outsl outsl
0732 static inline void outsl(unsigned long addr, const void *buffer,
0733              unsigned int count)
0734 {
0735     writesl(PCI_IOBASE + addr, buffer, count);
0736 }
0737 #endif
0738 
0739 #ifndef insb_p
0740 #define insb_p insb_p
0741 static inline void insb_p(unsigned long addr, void *buffer, unsigned int count)
0742 {
0743     insb(addr, buffer, count);
0744 }
0745 #endif
0746 
0747 #ifndef insw_p
0748 #define insw_p insw_p
0749 static inline void insw_p(unsigned long addr, void *buffer, unsigned int count)
0750 {
0751     insw(addr, buffer, count);
0752 }
0753 #endif
0754 
0755 #ifndef insl_p
0756 #define insl_p insl_p
0757 static inline void insl_p(unsigned long addr, void *buffer, unsigned int count)
0758 {
0759     insl(addr, buffer, count);
0760 }
0761 #endif
0762 
0763 #ifndef outsb_p
0764 #define outsb_p outsb_p
0765 static inline void outsb_p(unsigned long addr, const void *buffer,
0766                unsigned int count)
0767 {
0768     outsb(addr, buffer, count);
0769 }
0770 #endif
0771 
0772 #ifndef outsw_p
0773 #define outsw_p outsw_p
0774 static inline void outsw_p(unsigned long addr, const void *buffer,
0775                unsigned int count)
0776 {
0777     outsw(addr, buffer, count);
0778 }
0779 #endif
0780 
0781 #ifndef outsl_p
0782 #define outsl_p outsl_p
0783 static inline void outsl_p(unsigned long addr, const void *buffer,
0784                unsigned int count)
0785 {
0786     outsl(addr, buffer, count);
0787 }
0788 #endif
0789 
0790 #ifndef CONFIG_GENERIC_IOMAP
0791 #ifndef ioread8
0792 #define ioread8 ioread8
0793 static inline u8 ioread8(const volatile void __iomem *addr)
0794 {
0795     return readb(addr);
0796 }
0797 #endif
0798 
0799 #ifndef ioread16
0800 #define ioread16 ioread16
0801 static inline u16 ioread16(const volatile void __iomem *addr)
0802 {
0803     return readw(addr);
0804 }
0805 #endif
0806 
0807 #ifndef ioread32
0808 #define ioread32 ioread32
0809 static inline u32 ioread32(const volatile void __iomem *addr)
0810 {
0811     return readl(addr);
0812 }
0813 #endif
0814 
0815 #ifdef CONFIG_64BIT
0816 #ifndef ioread64
0817 #define ioread64 ioread64
0818 static inline u64 ioread64(const volatile void __iomem *addr)
0819 {
0820     return readq(addr);
0821 }
0822 #endif
0823 #endif /* CONFIG_64BIT */
0824 
0825 #ifndef iowrite8
0826 #define iowrite8 iowrite8
0827 static inline void iowrite8(u8 value, volatile void __iomem *addr)
0828 {
0829     writeb(value, addr);
0830 }
0831 #endif
0832 
0833 #ifndef iowrite16
0834 #define iowrite16 iowrite16
0835 static inline void iowrite16(u16 value, volatile void __iomem *addr)
0836 {
0837     writew(value, addr);
0838 }
0839 #endif
0840 
0841 #ifndef iowrite32
0842 #define iowrite32 iowrite32
0843 static inline void iowrite32(u32 value, volatile void __iomem *addr)
0844 {
0845     writel(value, addr);
0846 }
0847 #endif
0848 
0849 #ifdef CONFIG_64BIT
0850 #ifndef iowrite64
0851 #define iowrite64 iowrite64
0852 static inline void iowrite64(u64 value, volatile void __iomem *addr)
0853 {
0854     writeq(value, addr);
0855 }
0856 #endif
0857 #endif /* CONFIG_64BIT */
0858 
0859 #ifndef ioread16be
0860 #define ioread16be ioread16be
0861 static inline u16 ioread16be(const volatile void __iomem *addr)
0862 {
0863     return swab16(readw(addr));
0864 }
0865 #endif
0866 
0867 #ifndef ioread32be
0868 #define ioread32be ioread32be
0869 static inline u32 ioread32be(const volatile void __iomem *addr)
0870 {
0871     return swab32(readl(addr));
0872 }
0873 #endif
0874 
0875 #ifdef CONFIG_64BIT
0876 #ifndef ioread64be
0877 #define ioread64be ioread64be
0878 static inline u64 ioread64be(const volatile void __iomem *addr)
0879 {
0880     return swab64(readq(addr));
0881 }
0882 #endif
0883 #endif /* CONFIG_64BIT */
0884 
0885 #ifndef iowrite16be
0886 #define iowrite16be iowrite16be
0887 static inline void iowrite16be(u16 value, void volatile __iomem *addr)
0888 {
0889     writew(swab16(value), addr);
0890 }
0891 #endif
0892 
0893 #ifndef iowrite32be
0894 #define iowrite32be iowrite32be
0895 static inline void iowrite32be(u32 value, volatile void __iomem *addr)
0896 {
0897     writel(swab32(value), addr);
0898 }
0899 #endif
0900 
0901 #ifdef CONFIG_64BIT
0902 #ifndef iowrite64be
0903 #define iowrite64be iowrite64be
0904 static inline void iowrite64be(u64 value, volatile void __iomem *addr)
0905 {
0906     writeq(swab64(value), addr);
0907 }
0908 #endif
0909 #endif /* CONFIG_64BIT */
0910 
0911 #ifndef ioread8_rep
0912 #define ioread8_rep ioread8_rep
0913 static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer,
0914                    unsigned int count)
0915 {
0916     readsb(addr, buffer, count);
0917 }
0918 #endif
0919 
0920 #ifndef ioread16_rep
0921 #define ioread16_rep ioread16_rep
0922 static inline void ioread16_rep(const volatile void __iomem *addr,
0923                 void *buffer, unsigned int count)
0924 {
0925     readsw(addr, buffer, count);
0926 }
0927 #endif
0928 
0929 #ifndef ioread32_rep
0930 #define ioread32_rep ioread32_rep
0931 static inline void ioread32_rep(const volatile void __iomem *addr,
0932                 void *buffer, unsigned int count)
0933 {
0934     readsl(addr, buffer, count);
0935 }
0936 #endif
0937 
0938 #ifdef CONFIG_64BIT
0939 #ifndef ioread64_rep
0940 #define ioread64_rep ioread64_rep
0941 static inline void ioread64_rep(const volatile void __iomem *addr,
0942                 void *buffer, unsigned int count)
0943 {
0944     readsq(addr, buffer, count);
0945 }
0946 #endif
0947 #endif /* CONFIG_64BIT */
0948 
0949 #ifndef iowrite8_rep
0950 #define iowrite8_rep iowrite8_rep
0951 static inline void iowrite8_rep(volatile void __iomem *addr,
0952                 const void *buffer,
0953                 unsigned int count)
0954 {
0955     writesb(addr, buffer, count);
0956 }
0957 #endif
0958 
0959 #ifndef iowrite16_rep
0960 #define iowrite16_rep iowrite16_rep
0961 static inline void iowrite16_rep(volatile void __iomem *addr,
0962                  const void *buffer,
0963                  unsigned int count)
0964 {
0965     writesw(addr, buffer, count);
0966 }
0967 #endif
0968 
0969 #ifndef iowrite32_rep
0970 #define iowrite32_rep iowrite32_rep
0971 static inline void iowrite32_rep(volatile void __iomem *addr,
0972                  const void *buffer,
0973                  unsigned int count)
0974 {
0975     writesl(addr, buffer, count);
0976 }
0977 #endif
0978 
0979 #ifdef CONFIG_64BIT
0980 #ifndef iowrite64_rep
0981 #define iowrite64_rep iowrite64_rep
0982 static inline void iowrite64_rep(volatile void __iomem *addr,
0983                  const void *buffer,
0984                  unsigned int count)
0985 {
0986     writesq(addr, buffer, count);
0987 }
0988 #endif
0989 #endif /* CONFIG_64BIT */
0990 #endif /* CONFIG_GENERIC_IOMAP */
0991 
0992 #ifdef __KERNEL__
0993 
0994 #include <linux/vmalloc.h>
0995 #define __io_virt(x) ((void __force *)(x))
0996 
0997 /*
0998  * Change virtual addresses to physical addresses and vv.
0999  * These are pretty trivial
1000  */
1001 #ifndef virt_to_phys
1002 #define virt_to_phys virt_to_phys
1003 static inline unsigned long virt_to_phys(volatile void *address)
1004 {
1005     return __pa((unsigned long)address);
1006 }
1007 #endif
1008 
1009 #ifndef phys_to_virt
1010 #define phys_to_virt phys_to_virt
1011 static inline void *phys_to_virt(unsigned long address)
1012 {
1013     return __va(address);
1014 }
1015 #endif
1016 
1017 /**
1018  * DOC: ioremap() and ioremap_*() variants
1019  *
1020  * Architectures with an MMU are expected to provide ioremap() and iounmap()
1021  * themselves or rely on GENERIC_IOREMAP.  For NOMMU architectures we provide
1022  * a default nop-op implementation that expect that the physical address used
1023  * for MMIO are already marked as uncached, and can be used as kernel virtual
1024  * addresses.
1025  *
1026  * ioremap_wc() and ioremap_wt() can provide more relaxed caching attributes
1027  * for specific drivers if the architecture choses to implement them.  If they
1028  * are not implemented we fall back to plain ioremap. Conversely, ioremap_np()
1029  * can provide stricter non-posted write semantics if the architecture
1030  * implements them.
1031  */
1032 #ifndef CONFIG_MMU
1033 #ifndef ioremap
1034 #define ioremap ioremap
1035 static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
1036 {
1037     return (void __iomem *)(unsigned long)offset;
1038 }
1039 #endif
1040 
1041 #ifndef iounmap
1042 #define iounmap iounmap
1043 static inline void iounmap(volatile void __iomem *addr)
1044 {
1045 }
1046 #endif
1047 #elif defined(CONFIG_GENERIC_IOREMAP)
1048 #include <linux/pgtable.h>
1049 
1050 /*
1051  * Arch code can implement the following two hooks when using GENERIC_IOREMAP
1052  * ioremap_allowed() return a bool,
1053  *   - true means continue to remap
1054  *   - false means skip remap and return directly
1055  * iounmap_allowed() return a bool,
1056  *   - true means continue to vunmap
1057  *   - false means skip vunmap and return directly
1058  */
1059 #ifndef ioremap_allowed
1060 #define ioremap_allowed ioremap_allowed
1061 static inline bool ioremap_allowed(phys_addr_t phys_addr, size_t size,
1062                    unsigned long prot)
1063 {
1064     return true;
1065 }
1066 #endif
1067 
1068 #ifndef iounmap_allowed
1069 #define iounmap_allowed iounmap_allowed
1070 static inline bool iounmap_allowed(void *addr)
1071 {
1072     return true;
1073 }
1074 #endif
1075 
1076 void __iomem *ioremap_prot(phys_addr_t phys_addr, size_t size,
1077                unsigned long prot);
1078 void iounmap(volatile void __iomem *addr);
1079 
1080 static inline void __iomem *ioremap(phys_addr_t addr, size_t size)
1081 {
1082     /* _PAGE_IOREMAP needs to be supplied by the architecture */
1083     return ioremap_prot(addr, size, _PAGE_IOREMAP);
1084 }
1085 #endif /* !CONFIG_MMU || CONFIG_GENERIC_IOREMAP */
1086 
1087 #ifndef ioremap_wc
1088 #define ioremap_wc ioremap
1089 #endif
1090 
1091 #ifndef ioremap_wt
1092 #define ioremap_wt ioremap
1093 #endif
1094 
1095 /*
1096  * ioremap_uc is special in that we do require an explicit architecture
1097  * implementation.  In general you do not want to use this function in a
1098  * driver and use plain ioremap, which is uncached by default.  Similarly
1099  * architectures should not implement it unless they have a very good
1100  * reason.
1101  */
1102 #ifndef ioremap_uc
1103 #define ioremap_uc ioremap_uc
1104 static inline void __iomem *ioremap_uc(phys_addr_t offset, size_t size)
1105 {
1106     return NULL;
1107 }
1108 #endif
1109 
1110 /*
1111  * ioremap_np needs an explicit architecture implementation, as it
1112  * requests stronger semantics than regular ioremap(). Portable drivers
1113  * should instead use one of the higher-level abstractions, like
1114  * devm_ioremap_resource(), to choose the correct variant for any given
1115  * device and bus. Portable drivers with a good reason to want non-posted
1116  * write semantics should always provide an ioremap() fallback in case
1117  * ioremap_np() is not available.
1118  */
1119 #ifndef ioremap_np
1120 #define ioremap_np ioremap_np
1121 static inline void __iomem *ioremap_np(phys_addr_t offset, size_t size)
1122 {
1123     return NULL;
1124 }
1125 #endif
1126 
1127 #ifdef CONFIG_HAS_IOPORT_MAP
1128 #ifndef CONFIG_GENERIC_IOMAP
1129 #ifndef ioport_map
1130 #define ioport_map ioport_map
1131 static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
1132 {
1133     port &= IO_SPACE_LIMIT;
1134     return (port > MMIO_UPPER_LIMIT) ? NULL : PCI_IOBASE + port;
1135 }
1136 #define ARCH_HAS_GENERIC_IOPORT_MAP
1137 #endif
1138 
1139 #ifndef ioport_unmap
1140 #define ioport_unmap ioport_unmap
1141 static inline void ioport_unmap(void __iomem *p)
1142 {
1143 }
1144 #endif
1145 #else /* CONFIG_GENERIC_IOMAP */
1146 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
1147 extern void ioport_unmap(void __iomem *p);
1148 #endif /* CONFIG_GENERIC_IOMAP */
1149 #endif /* CONFIG_HAS_IOPORT_MAP */
1150 
1151 #ifndef CONFIG_GENERIC_IOMAP
1152 #ifndef pci_iounmap
1153 #define ARCH_WANTS_GENERIC_PCI_IOUNMAP
1154 #endif
1155 #endif
1156 
1157 #ifndef xlate_dev_mem_ptr
1158 #define xlate_dev_mem_ptr xlate_dev_mem_ptr
1159 static inline void *xlate_dev_mem_ptr(phys_addr_t addr)
1160 {
1161     return __va(addr);
1162 }
1163 #endif
1164 
1165 #ifndef unxlate_dev_mem_ptr
1166 #define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
1167 static inline void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr)
1168 {
1169 }
1170 #endif
1171 
1172 #ifndef memset_io
1173 #define memset_io memset_io
1174 /**
1175  * memset_io    Set a range of I/O memory to a constant value
1176  * @addr:   The beginning of the I/O-memory range to set
1177  * @val:    The value to set the memory to
1178  * @count:  The number of bytes to set
1179  *
1180  * Set a range of I/O memory to a given value.
1181  */
1182 static inline void memset_io(volatile void __iomem *addr, int value,
1183                  size_t size)
1184 {
1185     memset(__io_virt(addr), value, size);
1186 }
1187 #endif
1188 
1189 #ifndef memcpy_fromio
1190 #define memcpy_fromio memcpy_fromio
1191 /**
1192  * memcpy_fromio    Copy a block of data from I/O memory
1193  * @dst:        The (RAM) destination for the copy
1194  * @src:        The (I/O memory) source for the data
1195  * @count:      The number of bytes to copy
1196  *
1197  * Copy a block of data from I/O memory.
1198  */
1199 static inline void memcpy_fromio(void *buffer,
1200                  const volatile void __iomem *addr,
1201                  size_t size)
1202 {
1203     memcpy(buffer, __io_virt(addr), size);
1204 }
1205 #endif
1206 
1207 #ifndef memcpy_toio
1208 #define memcpy_toio memcpy_toio
1209 /**
1210  * memcpy_toio      Copy a block of data into I/O memory
1211  * @dst:        The (I/O memory) destination for the copy
1212  * @src:        The (RAM) source for the data
1213  * @count:      The number of bytes to copy
1214  *
1215  * Copy a block of data to I/O memory.
1216  */
1217 static inline void memcpy_toio(volatile void __iomem *addr, const void *buffer,
1218                    size_t size)
1219 {
1220     memcpy(__io_virt(addr), buffer, size);
1221 }
1222 #endif
1223 
1224 extern int devmem_is_allowed(unsigned long pfn);
1225 
1226 #endif /* __KERNEL__ */
1227 
1228 #endif /* __ASM_GENERIC_IO_H */
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