0001
0002
0003
0004 #define __ide_insw insw
0005 #define __ide_insl insl
0006 #define __ide_outsw outsw
0007 #define __ide_outsl outsl
0008
0009 static __inline__ void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
0010 {
0011 while (count--) {
0012 *(u16 *)addr = readw(port);
0013 addr += 2;
0014 }
0015 }
0016
0017 static __inline__ void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
0018 {
0019 while (count--) {
0020 *(u32 *)addr = readl(port);
0021 addr += 4;
0022 }
0023 }
0024
0025 static __inline__ void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
0026 {
0027 while (count--) {
0028 writew(*(u16 *)addr, port);
0029 addr += 2;
0030 }
0031 }
0032
0033 static __inline__ void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
0034 {
0035 while (count--) {
0036 writel(*(u32 *)addr, port);
0037 addr += 4;
0038 }
0039 }