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0010 #ifndef __ACTBL1_H__
0011 #define __ACTBL1_H__
0012
0013
0014
0015
0016
0017
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0019
0020
0021
0022
0023
0024
0025
0026
0027 #define ACPI_SIG_AEST "AEST"
0028 #define ACPI_SIG_ASF "ASF!"
0029 #define ACPI_SIG_BERT "BERT"
0030 #define ACPI_SIG_BGRT "BGRT"
0031 #define ACPI_SIG_BOOT "BOOT"
0032 #define ACPI_SIG_CEDT "CEDT"
0033 #define ACPI_SIG_CPEP "CPEP"
0034 #define ACPI_SIG_CSRT "CSRT"
0035 #define ACPI_SIG_DBG2 "DBG2"
0036 #define ACPI_SIG_DBGP "DBGP"
0037 #define ACPI_SIG_DMAR "DMAR"
0038 #define ACPI_SIG_DRTM "DRTM"
0039 #define ACPI_SIG_ECDT "ECDT"
0040 #define ACPI_SIG_EINJ "EINJ"
0041 #define ACPI_SIG_ERST "ERST"
0042 #define ACPI_SIG_FPDT "FPDT"
0043 #define ACPI_SIG_GTDT "GTDT"
0044 #define ACPI_SIG_HEST "HEST"
0045 #define ACPI_SIG_HMAT "HMAT"
0046 #define ACPI_SIG_HPET "HPET"
0047 #define ACPI_SIG_IBFT "IBFT"
0048
0049 #define ACPI_SIG_S3PT "S3PT"
0050 #define ACPI_SIG_PCCS "PCC"
0051
0052
0053
0054 #define ACPI_SIG_MATR "MATR"
0055 #define ACPI_SIG_MSDM "MSDM"
0056
0057
0058
0059
0060 #ifdef ACPI_UNDEFINED_TABLES
0061 #define ACPI_SIG_ATKG "ATKG"
0062 #define ACPI_SIG_GSCI "GSCI"
0063 #define ACPI_SIG_IEIT "IEIT"
0064 #endif
0065
0066
0067
0068
0069
0070 #pragma pack(1)
0071
0072
0073
0074
0075
0076
0077
0078
0079
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
0090
0091
0092 struct acpi_subtable_header {
0093 u8 type;
0094 u8 length;
0095 };
0096
0097
0098
0099 struct acpi_whea_header {
0100 u8 action;
0101 u8 instruction;
0102 u8 flags;
0103 u8 reserved;
0104 struct acpi_generic_address register_region;
0105 u64 value;
0106 u64 mask;
0107 };
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118 struct acpi_table_asf {
0119 struct acpi_table_header header;
0120 };
0121
0122
0123
0124 struct acpi_asf_header {
0125 u8 type;
0126 u8 reserved;
0127 u16 length;
0128 };
0129
0130
0131
0132 enum acpi_asf_type {
0133 ACPI_ASF_TYPE_INFO = 0,
0134 ACPI_ASF_TYPE_ALERT = 1,
0135 ACPI_ASF_TYPE_CONTROL = 2,
0136 ACPI_ASF_TYPE_BOOT = 3,
0137 ACPI_ASF_TYPE_ADDRESS = 4,
0138 ACPI_ASF_TYPE_RESERVED = 5
0139 };
0140
0141
0142
0143
0144
0145
0146
0147 struct acpi_asf_info {
0148 struct acpi_asf_header header;
0149 u8 min_reset_value;
0150 u8 min_poll_interval;
0151 u16 system_id;
0152 u32 mfg_id;
0153 u8 flags;
0154 u8 reserved2[3];
0155 };
0156
0157
0158
0159 #define ACPI_ASF_SMBUS_PROTOCOLS (1)
0160
0161
0162
0163 struct acpi_asf_alert {
0164 struct acpi_asf_header header;
0165 u8 assert_mask;
0166 u8 deassert_mask;
0167 u8 alerts;
0168 u8 data_length;
0169 };
0170
0171 struct acpi_asf_alert_data {
0172 u8 address;
0173 u8 command;
0174 u8 mask;
0175 u8 value;
0176 u8 sensor_type;
0177 u8 type;
0178 u8 offset;
0179 u8 source_type;
0180 u8 severity;
0181 u8 sensor_number;
0182 u8 entity;
0183 u8 instance;
0184 };
0185
0186
0187
0188 struct acpi_asf_remote {
0189 struct acpi_asf_header header;
0190 u8 controls;
0191 u8 data_length;
0192 u16 reserved2;
0193 };
0194
0195 struct acpi_asf_control_data {
0196 u8 function;
0197 u8 address;
0198 u8 command;
0199 u8 value;
0200 };
0201
0202
0203
0204 struct acpi_asf_rmcp {
0205 struct acpi_asf_header header;
0206 u8 capabilities[7];
0207 u8 completion_code;
0208 u32 enterprise_id;
0209 u8 command;
0210 u16 parameter;
0211 u16 boot_options;
0212 u16 oem_parameters;
0213 };
0214
0215
0216
0217 struct acpi_asf_address {
0218 struct acpi_asf_header header;
0219 u8 eprom_address;
0220 u8 devices;
0221 };
0222
0223
0224
0225
0226
0227
0228
0229
0230 struct acpi_table_bert {
0231 struct acpi_table_header header;
0232 u32 region_length;
0233 u64 address;
0234 };
0235
0236
0237
0238 struct acpi_bert_region {
0239 u32 block_status;
0240 u32 raw_data_offset;
0241 u32 raw_data_length;
0242 u32 data_length;
0243 u32 error_severity;
0244 };
0245
0246
0247
0248 #define ACPI_BERT_UNCORRECTABLE (1)
0249 #define ACPI_BERT_CORRECTABLE (1<<1)
0250 #define ACPI_BERT_MULTIPLE_UNCORRECTABLE (1<<2)
0251 #define ACPI_BERT_MULTIPLE_CORRECTABLE (1<<3)
0252 #define ACPI_BERT_ERROR_ENTRY_COUNT (0xFF<<4)
0253
0254
0255
0256 enum acpi_bert_error_severity {
0257 ACPI_BERT_ERROR_CORRECTABLE = 0,
0258 ACPI_BERT_ERROR_FATAL = 1,
0259 ACPI_BERT_ERROR_CORRECTED = 2,
0260 ACPI_BERT_ERROR_NONE = 3,
0261 ACPI_BERT_ERROR_RESERVED = 4
0262 };
0263
0264
0265
0266
0267
0268
0269
0270
0271
0272
0273
0274
0275
0276 struct acpi_table_bgrt {
0277 struct acpi_table_header header;
0278 u16 version;
0279 u8 status;
0280 u8 image_type;
0281 u64 image_address;
0282 u32 image_offset_x;
0283 u32 image_offset_y;
0284 };
0285
0286
0287
0288 #define ACPI_BGRT_DISPLAYED (1)
0289 #define ACPI_BGRT_ORIENTATION_OFFSET (3 << 1)
0290
0291
0292
0293
0294
0295
0296
0297
0298
0299
0300 struct acpi_table_boot {
0301 struct acpi_table_header header;
0302 u8 cmos_index;
0303 u8 reserved[3];
0304 };
0305
0306
0307
0308
0309
0310
0311
0312
0313
0314
0315 struct acpi_table_cedt {
0316 struct acpi_table_header header;
0317 };
0318
0319
0320
0321 struct acpi_cedt_header {
0322 u8 type;
0323 u8 reserved;
0324 u16 length;
0325 };
0326
0327
0328
0329 enum acpi_cedt_type {
0330 ACPI_CEDT_TYPE_CHBS = 0,
0331 ACPI_CEDT_TYPE_CFMWS = 1,
0332 ACPI_CEDT_TYPE_RESERVED = 2,
0333 };
0334
0335
0336
0337 #define ACPI_CEDT_CHBS_VERSION_CXL11 (0)
0338 #define ACPI_CEDT_CHBS_VERSION_CXL20 (1)
0339
0340
0341
0342 #define ACPI_CEDT_CHBS_LENGTH_CXL11 (0x2000)
0343 #define ACPI_CEDT_CHBS_LENGTH_CXL20 (0x10000)
0344
0345
0346
0347
0348
0349
0350
0351 struct acpi_cedt_chbs {
0352 struct acpi_cedt_header header;
0353 u32 uid;
0354 u32 cxl_version;
0355 u32 reserved;
0356 u64 base;
0357 u64 length;
0358 };
0359
0360
0361
0362 struct acpi_cedt_cfmws {
0363 struct acpi_cedt_header header;
0364 u32 reserved1;
0365 u64 base_hpa;
0366 u64 window_size;
0367 u8 interleave_ways;
0368 u8 interleave_arithmetic;
0369 u16 reserved2;
0370 u32 granularity;
0371 u16 restrictions;
0372 u16 qtg_id;
0373 u32 interleave_targets[];
0374 };
0375
0376 struct acpi_cedt_cfmws_target_element {
0377 u32 interleave_target;
0378 };
0379
0380
0381
0382 #define ACPI_CEDT_CFMWS_ARITHMETIC_MODULO (0)
0383
0384
0385
0386 #define ACPI_CEDT_CFMWS_RESTRICT_TYPE2 (1)
0387 #define ACPI_CEDT_CFMWS_RESTRICT_TYPE3 (1<<1)
0388 #define ACPI_CEDT_CFMWS_RESTRICT_VOLATILE (1<<2)
0389 #define ACPI_CEDT_CFMWS_RESTRICT_PMEM (1<<3)
0390 #define ACPI_CEDT_CFMWS_RESTRICT_FIXED (1<<4)
0391
0392
0393
0394
0395
0396
0397
0398
0399 struct acpi_table_cpep {
0400 struct acpi_table_header header;
0401 u64 reserved;
0402 };
0403
0404
0405
0406 struct acpi_cpep_polling {
0407 struct acpi_subtable_header header;
0408 u8 id;
0409 u8 eid;
0410 u32 interval;
0411 };
0412
0413
0414
0415
0416
0417
0418
0419
0420
0421
0422 struct acpi_table_csrt {
0423 struct acpi_table_header header;
0424 };
0425
0426
0427
0428 struct acpi_csrt_group {
0429 u32 length;
0430 u32 vendor_id;
0431 u32 subvendor_id;
0432 u16 device_id;
0433 u16 subdevice_id;
0434 u16 revision;
0435 u16 reserved;
0436 u32 shared_info_length;
0437
0438
0439 };
0440
0441
0442
0443 struct acpi_csrt_shared_info {
0444 u16 major_version;
0445 u16 minor_version;
0446 u32 mmio_base_low;
0447 u32 mmio_base_high;
0448 u32 gsi_interrupt;
0449 u8 interrupt_polarity;
0450 u8 interrupt_mode;
0451 u8 num_channels;
0452 u8 dma_address_width;
0453 u16 base_request_line;
0454 u16 num_handshake_signals;
0455 u32 max_block_size;
0456
0457
0458 };
0459
0460
0461
0462 struct acpi_csrt_descriptor {
0463 u32 length;
0464 u16 type;
0465 u16 subtype;
0466 u32 uid;
0467
0468
0469 };
0470
0471
0472
0473 #define ACPI_CSRT_TYPE_INTERRUPT 0x0001
0474 #define ACPI_CSRT_TYPE_TIMER 0x0002
0475 #define ACPI_CSRT_TYPE_DMA 0x0003
0476
0477
0478
0479 #define ACPI_CSRT_XRUPT_LINE 0x0000
0480 #define ACPI_CSRT_XRUPT_CONTROLLER 0x0001
0481 #define ACPI_CSRT_TIMER 0x0000
0482 #define ACPI_CSRT_DMA_CHANNEL 0x0000
0483 #define ACPI_CSRT_DMA_CONTROLLER 0x0001
0484
0485
0486
0487
0488
0489
0490
0491
0492
0493
0494 struct acpi_table_dbg2 {
0495 struct acpi_table_header header;
0496 u32 info_offset;
0497 u32 info_count;
0498 };
0499
0500 struct acpi_dbg2_header {
0501 u32 info_offset;
0502 u32 info_count;
0503 };
0504
0505
0506
0507 struct acpi_dbg2_device {
0508 u8 revision;
0509 u16 length;
0510 u8 register_count;
0511 u16 namepath_length;
0512 u16 namepath_offset;
0513 u16 oem_data_length;
0514 u16 oem_data_offset;
0515 u16 port_type;
0516 u16 port_subtype;
0517 u16 reserved;
0518 u16 base_address_offset;
0519 u16 address_size_offset;
0520
0521
0522
0523
0524
0525
0526
0527 };
0528
0529
0530
0531 #define ACPI_DBG2_SERIAL_PORT 0x8000
0532 #define ACPI_DBG2_1394_PORT 0x8001
0533 #define ACPI_DBG2_USB_PORT 0x8002
0534 #define ACPI_DBG2_NET_PORT 0x8003
0535
0536
0537
0538 #define ACPI_DBG2_16550_COMPATIBLE 0x0000
0539 #define ACPI_DBG2_16550_SUBSET 0x0001
0540 #define ACPI_DBG2_MAX311XE_SPI 0x0002
0541 #define ACPI_DBG2_ARM_PL011 0x0003
0542 #define ACPI_DBG2_MSM8X60 0x0004
0543 #define ACPI_DBG2_16550_NVIDIA 0x0005
0544 #define ACPI_DBG2_TI_OMAP 0x0006
0545 #define ACPI_DBG2_APM88XXXX 0x0008
0546 #define ACPI_DBG2_MSM8974 0x0009
0547 #define ACPI_DBG2_SAM5250 0x000A
0548 #define ACPI_DBG2_INTEL_USIF 0x000B
0549 #define ACPI_DBG2_IMX6 0x000C
0550 #define ACPI_DBG2_ARM_SBSA_32BIT 0x000D
0551 #define ACPI_DBG2_ARM_SBSA_GENERIC 0x000E
0552 #define ACPI_DBG2_ARM_DCC 0x000F
0553 #define ACPI_DBG2_BCM2835 0x0010
0554 #define ACPI_DBG2_SDM845_1_8432MHZ 0x0011
0555 #define ACPI_DBG2_16550_WITH_GAS 0x0012
0556 #define ACPI_DBG2_SDM845_7_372MHZ 0x0013
0557 #define ACPI_DBG2_INTEL_LPSS 0x0014
0558
0559 #define ACPI_DBG2_1394_STANDARD 0x0000
0560
0561 #define ACPI_DBG2_USB_XHCI 0x0000
0562 #define ACPI_DBG2_USB_EHCI 0x0001
0563
0564
0565
0566
0567
0568
0569
0570
0571
0572
0573 struct acpi_table_dbgp {
0574 struct acpi_table_header header;
0575 u8 type;
0576 u8 reserved[3];
0577 struct acpi_generic_address debug_port;
0578 };
0579
0580
0581
0582
0583
0584
0585
0586
0587
0588
0589
0590 struct acpi_table_dmar {
0591 struct acpi_table_header header;
0592 u8 width;
0593 u8 flags;
0594 u8 reserved[10];
0595 };
0596
0597
0598
0599 #define ACPI_DMAR_INTR_REMAP (1)
0600 #define ACPI_DMAR_X2APIC_OPT_OUT (1<<1)
0601 #define ACPI_DMAR_X2APIC_MODE (1<<2)
0602
0603
0604
0605 struct acpi_dmar_header {
0606 u16 type;
0607 u16 length;
0608 };
0609
0610
0611
0612 enum acpi_dmar_type {
0613 ACPI_DMAR_TYPE_HARDWARE_UNIT = 0,
0614 ACPI_DMAR_TYPE_RESERVED_MEMORY = 1,
0615 ACPI_DMAR_TYPE_ROOT_ATS = 2,
0616 ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3,
0617 ACPI_DMAR_TYPE_NAMESPACE = 4,
0618 ACPI_DMAR_TYPE_SATC = 5,
0619 ACPI_DMAR_TYPE_RESERVED = 6
0620 };
0621
0622
0623
0624 struct acpi_dmar_device_scope {
0625 u8 entry_type;
0626 u8 length;
0627 u16 reserved;
0628 u8 enumeration_id;
0629 u8 bus;
0630 };
0631
0632
0633
0634 enum acpi_dmar_scope_type {
0635 ACPI_DMAR_SCOPE_TYPE_NOT_USED = 0,
0636 ACPI_DMAR_SCOPE_TYPE_ENDPOINT = 1,
0637 ACPI_DMAR_SCOPE_TYPE_BRIDGE = 2,
0638 ACPI_DMAR_SCOPE_TYPE_IOAPIC = 3,
0639 ACPI_DMAR_SCOPE_TYPE_HPET = 4,
0640 ACPI_DMAR_SCOPE_TYPE_NAMESPACE = 5,
0641 ACPI_DMAR_SCOPE_TYPE_RESERVED = 6
0642 };
0643
0644 struct acpi_dmar_pci_path {
0645 u8 device;
0646 u8 function;
0647 };
0648
0649
0650
0651
0652
0653
0654
0655 struct acpi_dmar_hardware_unit {
0656 struct acpi_dmar_header header;
0657 u8 flags;
0658 u8 reserved;
0659 u16 segment;
0660 u64 address;
0661 };
0662
0663
0664
0665 #define ACPI_DMAR_INCLUDE_ALL (1)
0666
0667
0668
0669 struct acpi_dmar_reserved_memory {
0670 struct acpi_dmar_header header;
0671 u16 reserved;
0672 u16 segment;
0673 u64 base_address;
0674 u64 end_address;
0675 };
0676
0677
0678
0679 #define ACPI_DMAR_ALLOW_ALL (1)
0680
0681
0682
0683 struct acpi_dmar_atsr {
0684 struct acpi_dmar_header header;
0685 u8 flags;
0686 u8 reserved;
0687 u16 segment;
0688 };
0689
0690
0691
0692 #define ACPI_DMAR_ALL_PORTS (1)
0693
0694
0695
0696 struct acpi_dmar_rhsa {
0697 struct acpi_dmar_header header;
0698 u32 reserved;
0699 u64 base_address;
0700 u32 proximity_domain;
0701 };
0702
0703
0704
0705 struct acpi_dmar_andd {
0706 struct acpi_dmar_header header;
0707 u8 reserved[3];
0708 u8 device_number;
0709 char device_name[1];
0710 };
0711
0712
0713
0714 struct acpi_dmar_satc {
0715 struct acpi_dmar_header header;
0716 u8 flags;
0717 u8 reserved;
0718 u16 segment;
0719 };
0720
0721
0722
0723
0724
0725
0726
0727
0728 struct acpi_table_drtm {
0729 struct acpi_table_header header;
0730 u64 entry_base_address;
0731 u64 entry_length;
0732 u32 entry_address32;
0733 u64 entry_address64;
0734 u64 exit_address;
0735 u64 log_area_address;
0736 u32 log_area_length;
0737 u64 arch_dependent_address;
0738 u32 flags;
0739 };
0740
0741
0742
0743 #define ACPI_DRTM_ACCESS_ALLOWED (1)
0744 #define ACPI_DRTM_ENABLE_GAP_CODE (1<<1)
0745 #define ACPI_DRTM_INCOMPLETE_MEASUREMENTS (1<<2)
0746 #define ACPI_DRTM_AUTHORITY_ORDER (1<<3)
0747
0748
0749
0750 struct acpi_drtm_vtable_list {
0751 u32 validated_table_count;
0752 u64 validated_tables[1];
0753 };
0754
0755
0756
0757
0758
0759 struct acpi_drtm_resource {
0760 u8 size[7];
0761 u8 type;
0762 u64 address;
0763 };
0764
0765 struct acpi_drtm_resource_list {
0766 u32 resource_count;
0767 struct acpi_drtm_resource resources[1];
0768 };
0769
0770
0771
0772 struct acpi_drtm_dps_id {
0773 u32 dps_id_length;
0774 u8 dps_id[16];
0775 };
0776
0777
0778
0779
0780
0781
0782
0783
0784 struct acpi_table_ecdt {
0785 struct acpi_table_header header;
0786 struct acpi_generic_address control;
0787 struct acpi_generic_address data;
0788 u32 uid;
0789 u8 gpe;
0790 u8 id[1];
0791 };
0792
0793
0794
0795
0796
0797
0798
0799
0800 struct acpi_table_einj {
0801 struct acpi_table_header header;
0802 u32 header_length;
0803 u8 flags;
0804 u8 reserved[3];
0805 u32 entries;
0806 };
0807
0808
0809
0810 struct acpi_einj_entry {
0811 struct acpi_whea_header whea_header;
0812 };
0813
0814
0815
0816 #define ACPI_EINJ_PRESERVE (1)
0817
0818
0819
0820 enum acpi_einj_actions {
0821 ACPI_EINJ_BEGIN_OPERATION = 0,
0822 ACPI_EINJ_GET_TRIGGER_TABLE = 1,
0823 ACPI_EINJ_SET_ERROR_TYPE = 2,
0824 ACPI_EINJ_GET_ERROR_TYPE = 3,
0825 ACPI_EINJ_END_OPERATION = 4,
0826 ACPI_EINJ_EXECUTE_OPERATION = 5,
0827 ACPI_EINJ_CHECK_BUSY_STATUS = 6,
0828 ACPI_EINJ_GET_COMMAND_STATUS = 7,
0829 ACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS = 8,
0830 ACPI_EINJ_GET_EXECUTE_TIMINGS = 9,
0831 ACPI_EINJ_ACTION_RESERVED = 10,
0832 ACPI_EINJ_TRIGGER_ERROR = 0xFF
0833 };
0834
0835
0836
0837 enum acpi_einj_instructions {
0838 ACPI_EINJ_READ_REGISTER = 0,
0839 ACPI_EINJ_READ_REGISTER_VALUE = 1,
0840 ACPI_EINJ_WRITE_REGISTER = 2,
0841 ACPI_EINJ_WRITE_REGISTER_VALUE = 3,
0842 ACPI_EINJ_NOOP = 4,
0843 ACPI_EINJ_FLUSH_CACHELINE = 5,
0844 ACPI_EINJ_INSTRUCTION_RESERVED = 6
0845 };
0846
0847 struct acpi_einj_error_type_with_addr {
0848 u32 error_type;
0849 u32 vendor_struct_offset;
0850 u32 flags;
0851 u32 apic_id;
0852 u64 address;
0853 u64 range;
0854 u32 pcie_id;
0855 };
0856
0857 struct acpi_einj_vendor {
0858 u32 length;
0859 u32 pcie_id;
0860 u16 vendor_id;
0861 u16 device_id;
0862 u8 revision_id;
0863 u8 reserved[3];
0864 };
0865
0866
0867
0868 struct acpi_einj_trigger {
0869 u32 header_size;
0870 u32 revision;
0871 u32 table_size;
0872 u32 entry_count;
0873 };
0874
0875
0876
0877 enum acpi_einj_command_status {
0878 ACPI_EINJ_SUCCESS = 0,
0879 ACPI_EINJ_FAILURE = 1,
0880 ACPI_EINJ_INVALID_ACCESS = 2,
0881 ACPI_EINJ_STATUS_RESERVED = 3
0882 };
0883
0884
0885
0886 #define ACPI_EINJ_PROCESSOR_CORRECTABLE (1)
0887 #define ACPI_EINJ_PROCESSOR_UNCORRECTABLE (1<<1)
0888 #define ACPI_EINJ_PROCESSOR_FATAL (1<<2)
0889 #define ACPI_EINJ_MEMORY_CORRECTABLE (1<<3)
0890 #define ACPI_EINJ_MEMORY_UNCORRECTABLE (1<<4)
0891 #define ACPI_EINJ_MEMORY_FATAL (1<<5)
0892 #define ACPI_EINJ_PCIX_CORRECTABLE (1<<6)
0893 #define ACPI_EINJ_PCIX_UNCORRECTABLE (1<<7)
0894 #define ACPI_EINJ_PCIX_FATAL (1<<8)
0895 #define ACPI_EINJ_PLATFORM_CORRECTABLE (1<<9)
0896 #define ACPI_EINJ_PLATFORM_UNCORRECTABLE (1<<10)
0897 #define ACPI_EINJ_PLATFORM_FATAL (1<<11)
0898 #define ACPI_EINJ_VENDOR_DEFINED (1<<31)
0899
0900
0901
0902
0903
0904
0905
0906
0907 struct acpi_table_erst {
0908 struct acpi_table_header header;
0909 u32 header_length;
0910 u32 reserved;
0911 u32 entries;
0912 };
0913
0914
0915
0916 struct acpi_erst_entry {
0917 struct acpi_whea_header whea_header;
0918 };
0919
0920
0921
0922 #define ACPI_ERST_PRESERVE (1)
0923
0924
0925
0926 enum acpi_erst_actions {
0927 ACPI_ERST_BEGIN_WRITE = 0,
0928 ACPI_ERST_BEGIN_READ = 1,
0929 ACPI_ERST_BEGIN_CLEAR = 2,
0930 ACPI_ERST_END = 3,
0931 ACPI_ERST_SET_RECORD_OFFSET = 4,
0932 ACPI_ERST_EXECUTE_OPERATION = 5,
0933 ACPI_ERST_CHECK_BUSY_STATUS = 6,
0934 ACPI_ERST_GET_COMMAND_STATUS = 7,
0935 ACPI_ERST_GET_RECORD_ID = 8,
0936 ACPI_ERST_SET_RECORD_ID = 9,
0937 ACPI_ERST_GET_RECORD_COUNT = 10,
0938 ACPI_ERST_BEGIN_DUMMY_WRIITE = 11,
0939 ACPI_ERST_NOT_USED = 12,
0940 ACPI_ERST_GET_ERROR_RANGE = 13,
0941 ACPI_ERST_GET_ERROR_LENGTH = 14,
0942 ACPI_ERST_GET_ERROR_ATTRIBUTES = 15,
0943 ACPI_ERST_EXECUTE_TIMINGS = 16,
0944 ACPI_ERST_ACTION_RESERVED = 17
0945 };
0946
0947
0948
0949 enum acpi_erst_instructions {
0950 ACPI_ERST_READ_REGISTER = 0,
0951 ACPI_ERST_READ_REGISTER_VALUE = 1,
0952 ACPI_ERST_WRITE_REGISTER = 2,
0953 ACPI_ERST_WRITE_REGISTER_VALUE = 3,
0954 ACPI_ERST_NOOP = 4,
0955 ACPI_ERST_LOAD_VAR1 = 5,
0956 ACPI_ERST_LOAD_VAR2 = 6,
0957 ACPI_ERST_STORE_VAR1 = 7,
0958 ACPI_ERST_ADD = 8,
0959 ACPI_ERST_SUBTRACT = 9,
0960 ACPI_ERST_ADD_VALUE = 10,
0961 ACPI_ERST_SUBTRACT_VALUE = 11,
0962 ACPI_ERST_STALL = 12,
0963 ACPI_ERST_STALL_WHILE_TRUE = 13,
0964 ACPI_ERST_SKIP_NEXT_IF_TRUE = 14,
0965 ACPI_ERST_GOTO = 15,
0966 ACPI_ERST_SET_SRC_ADDRESS_BASE = 16,
0967 ACPI_ERST_SET_DST_ADDRESS_BASE = 17,
0968 ACPI_ERST_MOVE_DATA = 18,
0969 ACPI_ERST_INSTRUCTION_RESERVED = 19
0970 };
0971
0972
0973
0974 enum acpi_erst_command_status {
0975 ACPI_ERST_SUCCESS = 0,
0976 ACPI_ERST_NO_SPACE = 1,
0977 ACPI_ERST_NOT_AVAILABLE = 2,
0978 ACPI_ERST_FAILURE = 3,
0979 ACPI_ERST_RECORD_EMPTY = 4,
0980 ACPI_ERST_NOT_FOUND = 5,
0981 ACPI_ERST_STATUS_RESERVED = 6
0982 };
0983
0984
0985
0986 struct acpi_erst_info {
0987 u16 signature;
0988 u8 data[48];
0989 };
0990
0991
0992
0993
0994
0995
0996
0997
0998 struct acpi_table_fpdt {
0999 struct acpi_table_header header;
1000 };
1001
1002
1003
1004 struct acpi_fpdt_header {
1005 u16 type;
1006 u8 length;
1007 u8 revision;
1008 };
1009
1010
1011
1012 enum acpi_fpdt_type {
1013 ACPI_FPDT_TYPE_BOOT = 0,
1014 ACPI_FPDT_TYPE_S3PERF = 1
1015 };
1016
1017
1018
1019
1020
1021
1022
1023 struct acpi_fpdt_boot_pointer {
1024 struct acpi_fpdt_header header;
1025 u8 reserved[4];
1026 u64 address;
1027 };
1028
1029
1030
1031 struct acpi_fpdt_s3pt_pointer {
1032 struct acpi_fpdt_header header;
1033 u8 reserved[4];
1034 u64 address;
1035 };
1036
1037
1038
1039
1040
1041 struct acpi_table_s3pt {
1042 u8 signature[4];
1043 u32 length;
1044 };
1045
1046
1047
1048
1049
1050
1051
1052 enum acpi_s3pt_type {
1053 ACPI_S3PT_TYPE_RESUME = 0,
1054 ACPI_S3PT_TYPE_SUSPEND = 1,
1055 ACPI_FPDT_BOOT_PERFORMANCE = 2
1056 };
1057
1058 struct acpi_s3pt_resume {
1059 struct acpi_fpdt_header header;
1060 u32 resume_count;
1061 u64 full_resume;
1062 u64 average_resume;
1063 };
1064
1065 struct acpi_s3pt_suspend {
1066 struct acpi_fpdt_header header;
1067 u64 suspend_start;
1068 u64 suspend_end;
1069 };
1070
1071
1072
1073
1074 struct acpi_fpdt_boot {
1075 struct acpi_fpdt_header header;
1076 u8 reserved[4];
1077 u64 reset_end;
1078 u64 load_start;
1079 u64 startup_start;
1080 u64 exit_services_entry;
1081 u64 exit_services_exit;
1082 };
1083
1084
1085
1086
1087
1088
1089
1090
1091 struct acpi_table_gtdt {
1092 struct acpi_table_header header;
1093 u64 counter_block_addresss;
1094 u32 reserved;
1095 u32 secure_el1_interrupt;
1096 u32 secure_el1_flags;
1097 u32 non_secure_el1_interrupt;
1098 u32 non_secure_el1_flags;
1099 u32 virtual_timer_interrupt;
1100 u32 virtual_timer_flags;
1101 u32 non_secure_el2_interrupt;
1102 u32 non_secure_el2_flags;
1103 u64 counter_read_block_address;
1104 u32 platform_timer_count;
1105 u32 platform_timer_offset;
1106 };
1107
1108
1109
1110 #define ACPI_GTDT_INTERRUPT_MODE (1)
1111 #define ACPI_GTDT_INTERRUPT_POLARITY (1<<1)
1112 #define ACPI_GTDT_ALWAYS_ON (1<<2)
1113
1114 struct acpi_gtdt_el2 {
1115 u32 virtual_el2_timer_gsiv;
1116 u32 virtual_el2_timer_flags;
1117 };
1118
1119
1120
1121 struct acpi_gtdt_header {
1122 u8 type;
1123 u16 length;
1124 };
1125
1126
1127
1128 enum acpi_gtdt_type {
1129 ACPI_GTDT_TYPE_TIMER_BLOCK = 0,
1130 ACPI_GTDT_TYPE_WATCHDOG = 1,
1131 ACPI_GTDT_TYPE_RESERVED = 2
1132 };
1133
1134
1135
1136
1137
1138 struct acpi_gtdt_timer_block {
1139 struct acpi_gtdt_header header;
1140 u8 reserved;
1141 u64 block_address;
1142 u32 timer_count;
1143 u32 timer_offset;
1144 };
1145
1146
1147
1148 struct acpi_gtdt_timer_entry {
1149 u8 frame_number;
1150 u8 reserved[3];
1151 u64 base_address;
1152 u64 el0_base_address;
1153 u32 timer_interrupt;
1154 u32 timer_flags;
1155 u32 virtual_timer_interrupt;
1156 u32 virtual_timer_flags;
1157 u32 common_flags;
1158 };
1159
1160
1161
1162 #define ACPI_GTDT_GT_IRQ_MODE (1)
1163 #define ACPI_GTDT_GT_IRQ_POLARITY (1<<1)
1164
1165
1166
1167 #define ACPI_GTDT_GT_IS_SECURE_TIMER (1)
1168 #define ACPI_GTDT_GT_ALWAYS_ON (1<<1)
1169
1170
1171
1172 struct acpi_gtdt_watchdog {
1173 struct acpi_gtdt_header header;
1174 u8 reserved;
1175 u64 refresh_frame_address;
1176 u64 control_frame_address;
1177 u32 timer_interrupt;
1178 u32 timer_flags;
1179 };
1180
1181
1182
1183 #define ACPI_GTDT_WATCHDOG_IRQ_MODE (1)
1184 #define ACPI_GTDT_WATCHDOG_IRQ_POLARITY (1<<1)
1185 #define ACPI_GTDT_WATCHDOG_SECURE (1<<2)
1186
1187
1188
1189
1190
1191
1192
1193
1194 struct acpi_table_hest {
1195 struct acpi_table_header header;
1196 u32 error_source_count;
1197 };
1198
1199
1200
1201 struct acpi_hest_header {
1202 u16 type;
1203 u16 source_id;
1204 };
1205
1206
1207
1208 enum acpi_hest_types {
1209 ACPI_HEST_TYPE_IA32_CHECK = 0,
1210 ACPI_HEST_TYPE_IA32_CORRECTED_CHECK = 1,
1211 ACPI_HEST_TYPE_IA32_NMI = 2,
1212 ACPI_HEST_TYPE_NOT_USED3 = 3,
1213 ACPI_HEST_TYPE_NOT_USED4 = 4,
1214 ACPI_HEST_TYPE_NOT_USED5 = 5,
1215 ACPI_HEST_TYPE_AER_ROOT_PORT = 6,
1216 ACPI_HEST_TYPE_AER_ENDPOINT = 7,
1217 ACPI_HEST_TYPE_AER_BRIDGE = 8,
1218 ACPI_HEST_TYPE_GENERIC_ERROR = 9,
1219 ACPI_HEST_TYPE_GENERIC_ERROR_V2 = 10,
1220 ACPI_HEST_TYPE_IA32_DEFERRED_CHECK = 11,
1221 ACPI_HEST_TYPE_RESERVED = 12
1222 };
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232 struct acpi_hest_ia_error_bank {
1233 u8 bank_number;
1234 u8 clear_status_on_init;
1235 u8 status_format;
1236 u8 reserved;
1237 u32 control_register;
1238 u64 control_data;
1239 u32 status_register;
1240 u32 address_register;
1241 u32 misc_register;
1242 };
1243
1244
1245
1246 struct acpi_hest_aer_common {
1247 u16 reserved1;
1248 u8 flags;
1249 u8 enabled;
1250 u32 records_to_preallocate;
1251 u32 max_sections_per_record;
1252 u32 bus;
1253 u16 device;
1254 u16 function;
1255 u16 device_control;
1256 u16 reserved2;
1257 u32 uncorrectable_mask;
1258 u32 uncorrectable_severity;
1259 u32 correctable_mask;
1260 u32 advanced_capabilities;
1261 };
1262
1263
1264
1265 #define ACPI_HEST_FIRMWARE_FIRST (1)
1266 #define ACPI_HEST_GLOBAL (1<<1)
1267 #define ACPI_HEST_GHES_ASSIST (1<<2)
1268
1269
1270
1271
1272
1273
1274 #define ACPI_HEST_BUS(bus) ((bus) & 0xFF)
1275 #define ACPI_HEST_SEGMENT(bus) (((bus) >> 8) & 0xFFFF)
1276
1277
1278
1279 struct acpi_hest_notify {
1280 u8 type;
1281 u8 length;
1282 u16 config_write_enable;
1283 u32 poll_interval;
1284 u32 vector;
1285 u32 polling_threshold_value;
1286 u32 polling_threshold_window;
1287 u32 error_threshold_value;
1288 u32 error_threshold_window;
1289 };
1290
1291
1292
1293 enum acpi_hest_notify_types {
1294 ACPI_HEST_NOTIFY_POLLED = 0,
1295 ACPI_HEST_NOTIFY_EXTERNAL = 1,
1296 ACPI_HEST_NOTIFY_LOCAL = 2,
1297 ACPI_HEST_NOTIFY_SCI = 3,
1298 ACPI_HEST_NOTIFY_NMI = 4,
1299 ACPI_HEST_NOTIFY_CMCI = 5,
1300 ACPI_HEST_NOTIFY_MCE = 6,
1301 ACPI_HEST_NOTIFY_GPIO = 7,
1302 ACPI_HEST_NOTIFY_SEA = 8,
1303 ACPI_HEST_NOTIFY_SEI = 9,
1304 ACPI_HEST_NOTIFY_GSIV = 10,
1305 ACPI_HEST_NOTIFY_SOFTWARE_DELEGATED = 11,
1306 ACPI_HEST_NOTIFY_RESERVED = 12
1307 };
1308
1309
1310
1311 #define ACPI_HEST_TYPE (1)
1312 #define ACPI_HEST_POLL_INTERVAL (1<<1)
1313 #define ACPI_HEST_POLL_THRESHOLD_VALUE (1<<2)
1314 #define ACPI_HEST_POLL_THRESHOLD_WINDOW (1<<3)
1315 #define ACPI_HEST_ERR_THRESHOLD_VALUE (1<<4)
1316 #define ACPI_HEST_ERR_THRESHOLD_WINDOW (1<<5)
1317
1318
1319
1320
1321
1322
1323
1324 struct acpi_hest_ia_machine_check {
1325 struct acpi_hest_header header;
1326 u16 reserved1;
1327 u8 flags;
1328 u8 enabled;
1329 u32 records_to_preallocate;
1330 u32 max_sections_per_record;
1331 u64 global_capability_data;
1332 u64 global_control_data;
1333 u8 num_hardware_banks;
1334 u8 reserved3[7];
1335 };
1336
1337
1338
1339 struct acpi_hest_ia_corrected {
1340 struct acpi_hest_header header;
1341 u16 reserved1;
1342 u8 flags;
1343 u8 enabled;
1344 u32 records_to_preallocate;
1345 u32 max_sections_per_record;
1346 struct acpi_hest_notify notify;
1347 u8 num_hardware_banks;
1348 u8 reserved2[3];
1349 };
1350
1351
1352
1353 struct acpi_hest_ia_nmi {
1354 struct acpi_hest_header header;
1355 u32 reserved;
1356 u32 records_to_preallocate;
1357 u32 max_sections_per_record;
1358 u32 max_raw_data_length;
1359 };
1360
1361
1362
1363
1364
1365 struct acpi_hest_aer_root {
1366 struct acpi_hest_header header;
1367 struct acpi_hest_aer_common aer;
1368 u32 root_error_command;
1369 };
1370
1371
1372
1373 struct acpi_hest_aer {
1374 struct acpi_hest_header header;
1375 struct acpi_hest_aer_common aer;
1376 };
1377
1378
1379
1380 struct acpi_hest_aer_bridge {
1381 struct acpi_hest_header header;
1382 struct acpi_hest_aer_common aer;
1383 u32 uncorrectable_mask2;
1384 u32 uncorrectable_severity2;
1385 u32 advanced_capabilities2;
1386 };
1387
1388
1389
1390 struct acpi_hest_generic {
1391 struct acpi_hest_header header;
1392 u16 related_source_id;
1393 u8 reserved;
1394 u8 enabled;
1395 u32 records_to_preallocate;
1396 u32 max_sections_per_record;
1397 u32 max_raw_data_length;
1398 struct acpi_generic_address error_status_address;
1399 struct acpi_hest_notify notify;
1400 u32 error_block_length;
1401 };
1402
1403
1404
1405 struct acpi_hest_generic_v2 {
1406 struct acpi_hest_header header;
1407 u16 related_source_id;
1408 u8 reserved;
1409 u8 enabled;
1410 u32 records_to_preallocate;
1411 u32 max_sections_per_record;
1412 u32 max_raw_data_length;
1413 struct acpi_generic_address error_status_address;
1414 struct acpi_hest_notify notify;
1415 u32 error_block_length;
1416 struct acpi_generic_address read_ack_register;
1417 u64 read_ack_preserve;
1418 u64 read_ack_write;
1419 };
1420
1421
1422
1423 struct acpi_hest_generic_status {
1424 u32 block_status;
1425 u32 raw_data_offset;
1426 u32 raw_data_length;
1427 u32 data_length;
1428 u32 error_severity;
1429 };
1430
1431
1432
1433 #define ACPI_HEST_UNCORRECTABLE (1)
1434 #define ACPI_HEST_CORRECTABLE (1<<1)
1435 #define ACPI_HEST_MULTIPLE_UNCORRECTABLE (1<<2)
1436 #define ACPI_HEST_MULTIPLE_CORRECTABLE (1<<3)
1437 #define ACPI_HEST_ERROR_ENTRY_COUNT (0xFF<<4)
1438
1439
1440
1441 struct acpi_hest_generic_data {
1442 u8 section_type[16];
1443 u32 error_severity;
1444 u16 revision;
1445 u8 validation_bits;
1446 u8 flags;
1447 u32 error_data_length;
1448 u8 fru_id[16];
1449 u8 fru_text[20];
1450 };
1451
1452
1453
1454 struct acpi_hest_generic_data_v300 {
1455 u8 section_type[16];
1456 u32 error_severity;
1457 u16 revision;
1458 u8 validation_bits;
1459 u8 flags;
1460 u32 error_data_length;
1461 u8 fru_id[16];
1462 u8 fru_text[20];
1463 u64 time_stamp;
1464 };
1465
1466
1467
1468 #define ACPI_HEST_GEN_ERROR_RECOVERABLE 0
1469 #define ACPI_HEST_GEN_ERROR_FATAL 1
1470 #define ACPI_HEST_GEN_ERROR_CORRECTED 2
1471 #define ACPI_HEST_GEN_ERROR_NONE 3
1472
1473
1474
1475 #define ACPI_HEST_GEN_VALID_FRU_ID (1)
1476 #define ACPI_HEST_GEN_VALID_FRU_STRING (1<<1)
1477 #define ACPI_HEST_GEN_VALID_TIMESTAMP (1<<2)
1478
1479
1480
1481 struct acpi_hest_ia_deferred_check {
1482 struct acpi_hest_header header;
1483 u16 reserved1;
1484 u8 flags;
1485 u8 enabled;
1486 u32 records_to_preallocate;
1487 u32 max_sections_per_record;
1488 struct acpi_hest_notify notify;
1489 u8 num_hardware_banks;
1490 u8 reserved2[3];
1491 };
1492
1493
1494
1495
1496
1497
1498
1499
1500 struct acpi_table_hmat {
1501 struct acpi_table_header header;
1502 u32 reserved;
1503 };
1504
1505
1506
1507 enum acpi_hmat_type {
1508 ACPI_HMAT_TYPE_PROXIMITY = 0,
1509 ACPI_HMAT_TYPE_LOCALITY = 1,
1510 ACPI_HMAT_TYPE_CACHE = 2,
1511 ACPI_HMAT_TYPE_RESERVED = 3
1512 };
1513
1514 struct acpi_hmat_structure {
1515 u16 type;
1516 u16 reserved;
1517 u32 length;
1518 };
1519
1520
1521
1522
1523
1524
1525
1526 struct acpi_hmat_proximity_domain {
1527 struct acpi_hmat_structure header;
1528 u16 flags;
1529 u16 reserved1;
1530 u32 processor_PD;
1531 u32 memory_PD;
1532 u32 reserved2;
1533 u64 reserved3;
1534 u64 reserved4;
1535 };
1536
1537
1538
1539 #define ACPI_HMAT_PROCESSOR_PD_VALID (1)
1540 #define ACPI_HMAT_MEMORY_PD_VALID (1<<1)
1541 #define ACPI_HMAT_RESERVATION_HINT (1<<2)
1542
1543
1544
1545 struct acpi_hmat_locality {
1546 struct acpi_hmat_structure header;
1547 u8 flags;
1548 u8 data_type;
1549 u8 min_transfer_size;
1550 u8 reserved1;
1551 u32 number_of_initiator_Pds;
1552 u32 number_of_target_Pds;
1553 u32 reserved2;
1554 u64 entry_base_unit;
1555 };
1556
1557
1558
1559 #define ACPI_HMAT_MEMORY_HIERARCHY (0x0F)
1560
1561
1562
1563 #define ACPI_HMAT_MEMORY 0
1564 #define ACPI_HMAT_LAST_LEVEL_CACHE 1
1565 #define ACPI_HMAT_1ST_LEVEL_CACHE 2
1566 #define ACPI_HMAT_2ND_LEVEL_CACHE 3
1567 #define ACPI_HMAT_3RD_LEVEL_CACHE 4
1568 #define ACPI_HMAT_MINIMUM_XFER_SIZE 0x10
1569 #define ACPI_HMAT_NON_SEQUENTIAL_XFERS 0x20
1570
1571
1572
1573
1574 #define ACPI_HMAT_ACCESS_LATENCY 0
1575 #define ACPI_HMAT_READ_LATENCY 1
1576 #define ACPI_HMAT_WRITE_LATENCY 2
1577 #define ACPI_HMAT_ACCESS_BANDWIDTH 3
1578 #define ACPI_HMAT_READ_BANDWIDTH 4
1579 #define ACPI_HMAT_WRITE_BANDWIDTH 5
1580
1581
1582
1583 struct acpi_hmat_cache {
1584 struct acpi_hmat_structure header;
1585 u32 memory_PD;
1586 u32 reserved1;
1587 u64 cache_size;
1588 u32 cache_attributes;
1589 u16 reserved2;
1590 u16 number_of_SMBIOShandles;
1591 };
1592
1593
1594
1595 #define ACPI_HMAT_TOTAL_CACHE_LEVEL (0x0000000F)
1596 #define ACPI_HMAT_CACHE_LEVEL (0x000000F0)
1597 #define ACPI_HMAT_CACHE_ASSOCIATIVITY (0x00000F00)
1598 #define ACPI_HMAT_WRITE_POLICY (0x0000F000)
1599 #define ACPI_HMAT_CACHE_LINE_SIZE (0xFFFF0000)
1600
1601
1602
1603 #define ACPI_HMAT_CA_NONE (0)
1604 #define ACPI_HMAT_CA_DIRECT_MAPPED (1)
1605 #define ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING (2)
1606
1607
1608
1609 #define ACPI_HMAT_CP_NONE (0)
1610 #define ACPI_HMAT_CP_WB (1)
1611 #define ACPI_HMAT_CP_WT (2)
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623 struct acpi_table_hpet {
1624 struct acpi_table_header header;
1625 u32 id;
1626 struct acpi_generic_address address;
1627 u8 sequence;
1628 u16 minimum_tick;
1629 u8 flags;
1630 };
1631
1632
1633
1634 #define ACPI_HPET_PAGE_PROTECT_MASK (3)
1635
1636
1637
1638 enum acpi_hpet_page_protect {
1639 ACPI_HPET_NO_PAGE_PROTECT = 0,
1640 ACPI_HPET_PAGE_PROTECT4 = 1,
1641 ACPI_HPET_PAGE_PROTECT64 = 2
1642 };
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657 struct acpi_table_ibft {
1658 struct acpi_table_header header;
1659 u8 reserved[12];
1660 };
1661
1662
1663
1664 struct acpi_ibft_header {
1665 u8 type;
1666 u8 version;
1667 u16 length;
1668 u8 index;
1669 u8 flags;
1670 };
1671
1672
1673
1674 enum acpi_ibft_type {
1675 ACPI_IBFT_TYPE_NOT_USED = 0,
1676 ACPI_IBFT_TYPE_CONTROL = 1,
1677 ACPI_IBFT_TYPE_INITIATOR = 2,
1678 ACPI_IBFT_TYPE_NIC = 3,
1679 ACPI_IBFT_TYPE_TARGET = 4,
1680 ACPI_IBFT_TYPE_EXTENSIONS = 5,
1681 ACPI_IBFT_TYPE_RESERVED = 6
1682 };
1683
1684
1685
1686 struct acpi_ibft_control {
1687 struct acpi_ibft_header header;
1688 u16 extensions;
1689 u16 initiator_offset;
1690 u16 nic0_offset;
1691 u16 target0_offset;
1692 u16 nic1_offset;
1693 u16 target1_offset;
1694 };
1695
1696 struct acpi_ibft_initiator {
1697 struct acpi_ibft_header header;
1698 u8 sns_server[16];
1699 u8 slp_server[16];
1700 u8 primary_server[16];
1701 u8 secondary_server[16];
1702 u16 name_length;
1703 u16 name_offset;
1704 };
1705
1706 struct acpi_ibft_nic {
1707 struct acpi_ibft_header header;
1708 u8 ip_address[16];
1709 u8 subnet_mask_prefix;
1710 u8 origin;
1711 u8 gateway[16];
1712 u8 primary_dns[16];
1713 u8 secondary_dns[16];
1714 u8 dhcp[16];
1715 u16 vlan;
1716 u8 mac_address[6];
1717 u16 pci_address;
1718 u16 name_length;
1719 u16 name_offset;
1720 };
1721
1722 struct acpi_ibft_target {
1723 struct acpi_ibft_header header;
1724 u8 target_ip_address[16];
1725 u16 target_ip_socket;
1726 u8 target_boot_lun[8];
1727 u8 chap_type;
1728 u8 nic_association;
1729 u16 target_name_length;
1730 u16 target_name_offset;
1731 u16 chap_name_length;
1732 u16 chap_name_offset;
1733 u16 chap_secret_length;
1734 u16 chap_secret_offset;
1735 u16 reverse_chap_name_length;
1736 u16 reverse_chap_name_offset;
1737 u16 reverse_chap_secret_length;
1738 u16 reverse_chap_secret_offset;
1739 };
1740
1741
1742
1743 #pragma pack()
1744
1745 #endif