drivers/watchdog/via_wdt.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * VIA Chipset Watchdog Driver
0004  *
0005  * Copyright (C) 2011 Sigfox
0006  * Author: Marc Vertes <marc.vertes@sigfox.com>
0007  * Based on a preliminary version from Harald Welte <HaraldWelte@viatech.com>
0008  * Timer code by Wim Van Sebroeck <wim@iguana.be>
0009  *
0010  * Caveat: PnP must be enabled in BIOS to allow full access to watchdog
0011  * control registers. If not, the watchdog must be configured in BIOS manually.
0012  */
0013
0014 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0015
0016 #include <linux/device.h>
0017 #include <linux/io.h>
0018 #include <linux/jiffies.h>
0019 #include <linux/module.h>
0020 #include <linux/pci.h>
0021 #include <linux/timer.h>
0022 #include <linux/watchdog.h>
0023
0024 /* Configuration registers relative to the pci device */
0025 #define VIA_WDT_MMIO_BASE   0xe8    /* MMIO region base address */
0026 #define VIA_WDT_CONF        0xec    /* watchdog enable state */
0027
0028 /* Relevant bits for the VIA_WDT_CONF register */
0029 #define VIA_WDT_CONF_ENABLE 0x01    /* 1: enable watchdog */
0030 #define VIA_WDT_CONF_MMIO   0x02    /* 1: enable watchdog MMIO */
0031
0032 /*
0033  * The MMIO region contains the watchdog control register and the
0034  * hardware timer counter.
0035  */
0036 #define VIA_WDT_MMIO_LEN    8   /* MMIO region length in bytes */
0037 #define VIA_WDT_CTL     0   /* MMIO addr+0: state/control reg. */
0038 #define VIA_WDT_COUNT       4   /* MMIO addr+4: timer counter reg. */
0039
0040 /* Bits for the VIA_WDT_CTL register */
0041 #define VIA_WDT_RUNNING     0x01    /* 0: stop, 1: running */
0042 #define VIA_WDT_FIRED       0x02    /* 1: restarted by expired watchdog */
0043 #define VIA_WDT_PWROFF      0x04    /* 0: reset, 1: poweroff */
0044 #define VIA_WDT_DISABLED    0x08    /* 1: timer is disabled */
0045 #define VIA_WDT_TRIGGER     0x80    /* 1: start a new countdown */
0046
0047 /* Hardware heartbeat in seconds */
0048 #define WDT_HW_HEARTBEAT 1
0049
0050 /* Timer heartbeat (500ms) */
0051 #define WDT_HEARTBEAT   (HZ/2)  /* should be <= ((WDT_HW_HEARTBEAT*HZ)/2) */
0052
0053 /* User space timeout in seconds */
0054 #define WDT_TIMEOUT_MAX 1023    /* approx. 17 min. */
0055 #define WDT_TIMEOUT 60
0056 static int timeout = WDT_TIMEOUT;
0057 module_param(timeout, int, 0);
0058 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds, between 1 and 1023 "
0059     "(default = " __MODULE_STRING(WDT_TIMEOUT) ")");
0060
0061 static bool nowayout = WATCHDOG_NOWAYOUT;
0062 module_param(nowayout, bool, 0);
0063 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
0064     "(default = " __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
0065
0066 static struct watchdog_device wdt_dev;
0067 static struct resource wdt_res;
0068 static void __iomem *wdt_mem;
0069 static unsigned int mmio;
0070 static void wdt_timer_tick(struct timer_list *unused);
0071 static DEFINE_TIMER(timer, wdt_timer_tick);
0072                     /* The timer that pings the watchdog */
0073 static unsigned long next_heartbeat;    /* the next_heartbeat for the timer */
0074
0075 static inline void wdt_reset(void)
0076 {
0077     unsigned int ctl = readl(wdt_mem);
0078
0079     writel(ctl | VIA_WDT_TRIGGER, wdt_mem);
0080 }
0081
0082 /*
0083  * Timer tick: the timer will make sure that the watchdog timer hardware
0084  * is being reset in time. The conditions to do this are:
0085  *  1) the watchdog timer has been started and /dev/watchdog is open
0086  *     and there is still time left before userspace should send the
0087  *     next heartbeat/ping. (note: the internal heartbeat is much smaller
0088  *     then the external/userspace heartbeat).
0089  *  2) the watchdog timer has been stopped by userspace.
0090  */
0091 static void wdt_timer_tick(struct timer_list *unused)
0092 {
0093     if (time_before(jiffies, next_heartbeat) ||
0094        (!watchdog_active(&wdt_dev))) {
0095         wdt_reset();
0096         mod_timer(&timer, jiffies + WDT_HEARTBEAT);
0097     } else
0098         pr_crit("I will reboot your machine !\n");
0099 }
0100
0101 static int wdt_ping(struct watchdog_device *wdd)
0102 {
0103     /* calculate when the next userspace timeout will be */
0104     next_heartbeat = jiffies + wdd->timeout * HZ;
0105     return 0;
0106 }
0107
0108 static int wdt_start(struct watchdog_device *wdd)
0109 {
0110     unsigned int ctl = readl(wdt_mem);
0111
0112     writel(wdd->timeout, wdt_mem + VIA_WDT_COUNT);
0113     writel(ctl | VIA_WDT_RUNNING | VIA_WDT_TRIGGER, wdt_mem);
0114     wdt_ping(wdd);
0115     mod_timer(&timer, jiffies + WDT_HEARTBEAT);
0116     return 0;
0117 }
0118
0119 static int wdt_stop(struct watchdog_device *wdd)
0120 {
0121     unsigned int ctl = readl(wdt_mem);
0122
0123     writel(ctl & ~VIA_WDT_RUNNING, wdt_mem);
0124     return 0;
0125 }
0126
0127 static int wdt_set_timeout(struct watchdog_device *wdd,
0128                unsigned int new_timeout)
0129 {
0130     writel(new_timeout, wdt_mem + VIA_WDT_COUNT);
0131     wdd->timeout = new_timeout;
0132     return 0;
0133 }
0134
0135 static const struct watchdog_info wdt_info = {
0136     .identity = "VIA watchdog",
0137     .options =  WDIOF_CARDRESET |
0138             WDIOF_SETTIMEOUT |
0139             WDIOF_MAGICCLOSE |
0140             WDIOF_KEEPALIVEPING,
0141 };
0142
0143 static const struct watchdog_ops wdt_ops = {
0144     .owner =    THIS_MODULE,
0145     .start =    wdt_start,
0146     .stop =     wdt_stop,
0147     .ping =     wdt_ping,
0148     .set_timeout =  wdt_set_timeout,
0149 };
0150
0151 static struct watchdog_device wdt_dev = {
0152     .info =     &wdt_info,
0153     .ops =      &wdt_ops,
0154     .min_timeout =  1,
0155     .max_timeout =  WDT_TIMEOUT_MAX,
0156 };
0157
0158 static int wdt_probe(struct pci_dev *pdev,
0159                    const struct pci_device_id *ent)
0160 {
0161     unsigned char conf;
0162     int ret = -ENODEV;
0163
0164     if (pci_enable_device(pdev)) {
0165         dev_err(&pdev->dev, "cannot enable PCI device\n");
0166         return -ENODEV;
0167     }
0168
0169     /*
0170      * Allocate a MMIO region which contains watchdog control register
0171      * and counter, then configure the watchdog to use this region.
0172      * This is possible only if PnP is properly enabled in BIOS.
0173      * If not, the watchdog must be configured in BIOS manually.
0174      */
0175     if (allocate_resource(&iomem_resource, &wdt_res, VIA_WDT_MMIO_LEN,
0176                   0xf0000000, 0xffffff00, 0xff, NULL, NULL)) {
0177         dev_err(&pdev->dev, "MMIO allocation failed\n");
0178         goto err_out_disable_device;
0179     }
0180
0181     pci_write_config_dword(pdev, VIA_WDT_MMIO_BASE, wdt_res.start);
0182     pci_read_config_byte(pdev, VIA_WDT_CONF, &conf);
0183     conf |= VIA_WDT_CONF_ENABLE | VIA_WDT_CONF_MMIO;
0184     pci_write_config_byte(pdev, VIA_WDT_CONF, conf);
0185
0186     pci_read_config_dword(pdev, VIA_WDT_MMIO_BASE, &mmio);
0187     if (mmio) {
0188         dev_info(&pdev->dev, "VIA Chipset watchdog MMIO: %x\n", mmio);
0189     } else {
0190         dev_err(&pdev->dev, "MMIO setting failed. Check BIOS.\n");
0191         goto err_out_resource;
0192     }
0193
0194     if (!request_mem_region(mmio, VIA_WDT_MMIO_LEN, "via_wdt")) {
0195         dev_err(&pdev->dev, "MMIO region busy\n");
0196         goto err_out_resource;
0197     }
0198
0199     wdt_mem = ioremap(mmio, VIA_WDT_MMIO_LEN);
0200     if (wdt_mem == NULL) {
0201         dev_err(&pdev->dev, "cannot remap VIA wdt MMIO registers\n");
0202         goto err_out_release;
0203     }
0204
0205     if (timeout < 1 || timeout > WDT_TIMEOUT_MAX)
0206         timeout = WDT_TIMEOUT;
0207
0208     wdt_dev.timeout = timeout;
0209     wdt_dev.parent = &pdev->dev;
0210     watchdog_set_nowayout(&wdt_dev, nowayout);
0211     if (readl(wdt_mem) & VIA_WDT_FIRED)
0212         wdt_dev.bootstatus |= WDIOF_CARDRESET;
0213
0214     ret = watchdog_register_device(&wdt_dev);
0215     if (ret)
0216         goto err_out_iounmap;
0217
0218     /* start triggering, in case of watchdog already enabled by BIOS */
0219     mod_timer(&timer, jiffies + WDT_HEARTBEAT);
0220     return 0;
0221
0222 err_out_iounmap:
0223     iounmap(wdt_mem);
0224 err_out_release:
0225     release_mem_region(mmio, VIA_WDT_MMIO_LEN);
0226 err_out_resource:
0227     release_resource(&wdt_res);
0228 err_out_disable_device:
0229     pci_disable_device(pdev);
0230     return ret;
0231 }
0232
0233 static void wdt_remove(struct pci_dev *pdev)
0234 {
0235     watchdog_unregister_device(&wdt_dev);
0236     del_timer_sync(&timer);
0237     iounmap(wdt_mem);
0238     release_mem_region(mmio, VIA_WDT_MMIO_LEN);
0239     release_resource(&wdt_res);
0240     pci_disable_device(pdev);
0241 }
0242
0243 static const struct pci_device_id wdt_pci_table[] = {
0244     { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CX700) },
0245     { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX800) },
0246     { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855) },
0247     { 0 }
0248 };
0249
0250 static struct pci_driver wdt_driver = {
0251     .name       = "via_wdt",
0252     .id_table   = wdt_pci_table,
0253     .probe      = wdt_probe,
0254     .remove     = wdt_remove,
0255 };
0256
0257 module_pci_driver(wdt_driver);
0258
0259 MODULE_AUTHOR("Marc Vertes");
0260 MODULE_DESCRIPTION("Driver for watchdog timer on VIA chipset");
0261 MODULE_LICENSE("GPL");