drivers/watchdog/stm32_iwdg.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for STM32 Independent Watchdog
0004  *
0005  * Copyright (C) STMicroelectronics 2017
0006  * Author: Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
0007  *
0008  * This driver is based on tegra_wdt.c
0009  *
0010  */
0011
0012 #include <linux/clk.h>
0013 #include <linux/delay.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/io.h>
0016 #include <linux/iopoll.h>
0017 #include <linux/kernel.h>
0018 #include <linux/module.h>
0019 #include <linux/of.h>
0020 #include <linux/of_device.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/watchdog.h>
0023
0024 /* IWDG registers */
0025 #define IWDG_KR     0x00 /* Key register */
0026 #define IWDG_PR     0x04 /* Prescaler Register */
0027 #define IWDG_RLR    0x08 /* ReLoad Register */
0028 #define IWDG_SR     0x0C /* Status Register */
0029 #define IWDG_WINR   0x10 /* Windows Register */
0030
0031 /* IWDG_KR register bit mask */
0032 #define KR_KEY_RELOAD   0xAAAA /* reload counter enable */
0033 #define KR_KEY_ENABLE   0xCCCC /* peripheral enable */
0034 #define KR_KEY_EWA  0x5555 /* write access enable */
0035 #define KR_KEY_DWA  0x0000 /* write access disable */
0036
0037 /* IWDG_PR register */
0038 #define PR_SHIFT    2
0039 #define PR_MIN      BIT(PR_SHIFT)
0040
0041 /* IWDG_RLR register values */
0042 #define RLR_MIN     0x2     /* min value recommended */
0043 #define RLR_MAX     GENMASK(11, 0)  /* max value of reload register */
0044
0045 /* IWDG_SR register bit mask */
0046 #define SR_PVU  BIT(0) /* Watchdog prescaler value update */
0047 #define SR_RVU  BIT(1) /* Watchdog counter reload value update */
0048
0049 /* set timeout to 100000 us */
0050 #define TIMEOUT_US  100000
0051 #define SLEEP_US    1000
0052
0053 struct stm32_iwdg_data {
0054     bool has_pclk;
0055     u32 max_prescaler;
0056 };
0057
0058 static const struct stm32_iwdg_data stm32_iwdg_data = {
0059     .has_pclk = false,
0060     .max_prescaler = 256,
0061 };
0062
0063 static const struct stm32_iwdg_data stm32mp1_iwdg_data = {
0064     .has_pclk = true,
0065     .max_prescaler = 1024,
0066 };
0067
0068 struct stm32_iwdg {
0069     struct watchdog_device  wdd;
0070     const struct stm32_iwdg_data *data;
0071     void __iomem        *regs;
0072     struct clk      *clk_lsi;
0073     struct clk      *clk_pclk;
0074     unsigned int        rate;
0075 };
0076
0077 static inline u32 reg_read(void __iomem *base, u32 reg)
0078 {
0079     return readl_relaxed(base + reg);
0080 }
0081
0082 static inline void reg_write(void __iomem *base, u32 reg, u32 val)
0083 {
0084     writel_relaxed(val, base + reg);
0085 }
0086
0087 static int stm32_iwdg_start(struct watchdog_device *wdd)
0088 {
0089     struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
0090     u32 tout, presc, iwdg_rlr, iwdg_pr, iwdg_sr;
0091     int ret;
0092
0093     dev_dbg(wdd->parent, "%s\n", __func__);
0094
0095     tout = clamp_t(unsigned int, wdd->timeout,
0096                wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000);
0097
0098     presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1);
0099
0100     /* The prescaler is align on power of 2 and start at 2 ^ PR_SHIFT. */
0101     presc = roundup_pow_of_two(presc);
0102     iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT;
0103     iwdg_rlr = ((tout * wdt->rate) / presc) - 1;
0104
0105     /* enable write access */
0106     reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
0107
0108     /* set prescaler & reload registers */
0109     reg_write(wdt->regs, IWDG_PR, iwdg_pr);
0110     reg_write(wdt->regs, IWDG_RLR, iwdg_rlr);
0111     reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
0112
0113     /* wait for the registers to be updated (max 100ms) */
0114     ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr,
0115                      !(iwdg_sr & (SR_PVU | SR_RVU)),
0116                      SLEEP_US, TIMEOUT_US);
0117     if (ret) {
0118         dev_err(wdd->parent, "Fail to set prescaler, reload regs\n");
0119         return ret;
0120     }
0121
0122     /* reload watchdog */
0123     reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
0124
0125     return 0;
0126 }
0127
0128 static int stm32_iwdg_ping(struct watchdog_device *wdd)
0129 {
0130     struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
0131
0132     dev_dbg(wdd->parent, "%s\n", __func__);
0133
0134     /* reload watchdog */
0135     reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
0136
0137     return 0;
0138 }
0139
0140 static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
0141                   unsigned int timeout)
0142 {
0143     dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);
0144
0145     wdd->timeout = timeout;
0146
0147     if (watchdog_active(wdd))
0148         return stm32_iwdg_start(wdd);
0149
0150     return 0;
0151 }
0152
0153 static void stm32_clk_disable_unprepare(void *data)
0154 {
0155     clk_disable_unprepare(data);
0156 }
0157
0158 static int stm32_iwdg_clk_init(struct platform_device *pdev,
0159                    struct stm32_iwdg *wdt)
0160 {
0161     struct device *dev = &pdev->dev;
0162     u32 ret;
0163
0164     wdt->clk_lsi = devm_clk_get(dev, "lsi");
0165     if (IS_ERR(wdt->clk_lsi))
0166         return dev_err_probe(dev, PTR_ERR(wdt->clk_lsi), "Unable to get lsi clock\n");
0167
0168     /* optional peripheral clock */
0169     if (wdt->data->has_pclk) {
0170         wdt->clk_pclk = devm_clk_get(dev, "pclk");
0171         if (IS_ERR(wdt->clk_pclk))
0172             return dev_err_probe(dev, PTR_ERR(wdt->clk_pclk),
0173                          "Unable to get pclk clock\n");
0174
0175         ret = clk_prepare_enable(wdt->clk_pclk);
0176         if (ret) {
0177             dev_err(dev, "Unable to prepare pclk clock\n");
0178             return ret;
0179         }
0180         ret = devm_add_action_or_reset(dev,
0181                            stm32_clk_disable_unprepare,
0182                            wdt->clk_pclk);
0183         if (ret)
0184             return ret;
0185     }
0186
0187     ret = clk_prepare_enable(wdt->clk_lsi);
0188     if (ret) {
0189         dev_err(dev, "Unable to prepare lsi clock\n");
0190         return ret;
0191     }
0192     ret = devm_add_action_or_reset(dev, stm32_clk_disable_unprepare,
0193                        wdt->clk_lsi);
0194     if (ret)
0195         return ret;
0196
0197     wdt->rate = clk_get_rate(wdt->clk_lsi);
0198
0199     return 0;
0200 }
0201
0202 static const struct watchdog_info stm32_iwdg_info = {
0203     .options    = WDIOF_SETTIMEOUT |
0204               WDIOF_MAGICCLOSE |
0205               WDIOF_KEEPALIVEPING,
0206     .identity   = "STM32 Independent Watchdog",
0207 };
0208
0209 static const struct watchdog_ops stm32_iwdg_ops = {
0210     .owner      = THIS_MODULE,
0211     .start      = stm32_iwdg_start,
0212     .ping       = stm32_iwdg_ping,
0213     .set_timeout    = stm32_iwdg_set_timeout,
0214 };
0215
0216 static const struct of_device_id stm32_iwdg_of_match[] = {
0217     { .compatible = "st,stm32-iwdg", .data = &stm32_iwdg_data },
0218     { .compatible = "st,stm32mp1-iwdg", .data = &stm32mp1_iwdg_data },
0219     { /* end node */ }
0220 };
0221 MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
0222
0223 static int stm32_iwdg_probe(struct platform_device *pdev)
0224 {
0225     struct device *dev = &pdev->dev;
0226     struct watchdog_device *wdd;
0227     struct stm32_iwdg *wdt;
0228     int ret;
0229
0230     wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
0231     if (!wdt)
0232         return -ENOMEM;
0233
0234     wdt->data = of_device_get_match_data(&pdev->dev);
0235     if (!wdt->data)
0236         return -ENODEV;
0237
0238     /* This is the timer base. */
0239     wdt->regs = devm_platform_ioremap_resource(pdev, 0);
0240     if (IS_ERR(wdt->regs))
0241         return PTR_ERR(wdt->regs);
0242
0243     ret = stm32_iwdg_clk_init(pdev, wdt);
0244     if (ret)
0245         return ret;
0246
0247     /* Initialize struct watchdog_device. */
0248     wdd = &wdt->wdd;
0249     wdd->parent = dev;
0250     wdd->info = &stm32_iwdg_info;
0251     wdd->ops = &stm32_iwdg_ops;
0252     wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate);
0253     wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler *
0254                     1000) / wdt->rate;
0255
0256     watchdog_set_drvdata(wdd, wdt);
0257     watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
0258     watchdog_init_timeout(wdd, 0, dev);
0259
0260     /*
0261      * In case of CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is set
0262      * (Means U-Boot/bootloaders leaves the watchdog running)
0263      * When we get here we should make a decision to prevent
0264      * any side effects before user space daemon will take care of it.
0265      * The best option, taking into consideration that there is no
0266      * way to read values back from hardware, is to enforce watchdog
0267      * being run with deterministic values.
0268      */
0269     if (IS_ENABLED(CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED)) {
0270         ret = stm32_iwdg_start(wdd);
0271         if (ret)
0272             return ret;
0273
0274         /* Make sure the watchdog is serviced */
0275         set_bit(WDOG_HW_RUNNING, &wdd->status);
0276     }
0277
0278     ret = devm_watchdog_register_device(dev, wdd);
0279     if (ret)
0280         return ret;
0281
0282     platform_set_drvdata(pdev, wdt);
0283
0284     return 0;
0285 }
0286
0287 static struct platform_driver stm32_iwdg_driver = {
0288     .probe      = stm32_iwdg_probe,
0289     .driver = {
0290         .name   = "iwdg",
0291         .of_match_table = of_match_ptr(stm32_iwdg_of_match),
0292     },
0293 };
0294 module_platform_driver(stm32_iwdg_driver);
0295
0296 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
0297 MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");
0298 MODULE_LICENSE("GPL v2");