drivers/watchdog/sp5100_tco.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  *  sp5100_tco: TCO timer driver for sp5100 chipsets.
0004  *
0005  *  (c) Copyright 2009 Google Inc., All Rights Reserved.
0006  *
0007  *  TCO timer driver for sp5100 chipsets
0008  */
0009
0010 #include <linux/bitops.h>
0011
0012 /*
0013  * Some address definitions for the Watchdog
0014  */
0015 #define SP5100_WDT_MEM_MAP_SIZE     0x08
0016 #define SP5100_WDT_CONTROL(base)    ((base) + 0x00) /* Watchdog Control */
0017 #define SP5100_WDT_COUNT(base)      ((base) + 0x04) /* Watchdog Count */
0018
0019 #define SP5100_WDT_START_STOP_BIT   BIT(0)
0020 #define SP5100_WDT_FIRED        BIT(1)
0021 #define SP5100_WDT_ACTION_RESET     BIT(2)
0022 #define SP5100_WDT_DISABLED     BIT(3)
0023 #define SP5100_WDT_TRIGGER_BIT      BIT(7)
0024
0025 #define SP5100_PM_IOPORTS_SIZE      0x02
0026
0027 /*
0028  * These two IO registers are hardcoded and there doesn't seem to be a way to
0029  * read them from a register.
0030  */
0031
0032 /*  For SP5100/SB7x0/SB8x0 chipset */
0033 #define SP5100_IO_PM_INDEX_REG      0xCD6
0034 #define SP5100_IO_PM_DATA_REG       0xCD7
0035
0036 /* For SP5100/SB7x0 chipset */
0037 #define SP5100_SB_RESOURCE_MMIO_BASE    0x9C
0038
0039 #define SP5100_PM_WATCHDOG_CONTROL  0x69
0040 #define SP5100_PM_WATCHDOG_BASE     0x6C
0041
0042 #define SP5100_PCI_WATCHDOG_MISC_REG    0x41
0043 #define SP5100_PCI_WATCHDOG_DECODE_EN   BIT(3)
0044
0045 #define SP5100_PM_WATCHDOG_DISABLE  ((u8)BIT(0))
0046 #define SP5100_PM_WATCHDOG_SECOND_RES   GENMASK(2, 1)
0047
0048 #define SP5100_DEVNAME          "SP5100 TCO"
0049
0050 /*  For SB8x0(or later) chipset */
0051 #define SB800_PM_ACPI_MMIO_EN       0x24
0052 #define SB800_PM_WATCHDOG_CONTROL   0x48
0053 #define SB800_PM_WATCHDOG_BASE      0x48
0054 #define SB800_PM_WATCHDOG_CONFIG    0x4C
0055
0056 #define SB800_PCI_WATCHDOG_DECODE_EN    BIT(0)
0057 #define SB800_PM_WATCHDOG_DISABLE   ((u8)BIT(1))
0058 #define SB800_PM_WATCHDOG_SECOND_RES    GENMASK(1, 0)
0059 #define SB800_ACPI_MMIO_DECODE_EN   BIT(0)
0060 #define SB800_ACPI_MMIO_SEL     BIT(1)
0061 #define SB800_ACPI_MMIO_MASK        GENMASK(1, 0)
0062
0063 #define SB800_PM_WDT_MMIO_OFFSET    0xB00
0064
0065 #define SB800_DEVNAME           "SB800 TCO"
0066
0067 /* For recent chips with embedded FCH (rev 40+) */
0068
0069 #define EFCH_PM_DECODEEN        0x00
0070
0071 #define EFCH_PM_DECODEEN_WDT_TMREN  BIT(7)
0072
0073
0074 #define EFCH_PM_DECODEEN3       0x03
0075 #define EFCH_PM_DECODEEN_SECOND_RES GENMASK(1, 0)
0076 #define EFCH_PM_WATCHDOG_DISABLE    ((u8)GENMASK(3, 2))
0077
0078 /* WDT MMIO if enabled with PM00_DECODEEN_WDT_TMREN */
0079 #define EFCH_PM_WDT_ADDR        0xfeb00000
0080
0081 #define EFCH_PM_ISACONTROL      0x04
0082
0083 #define EFCH_PM_ISACONTROL_MMIOEN   BIT(1)
0084
0085 #define EFCH_PM_ACPI_MMIO_ADDR      0xfed80000
0086 #define EFCH_PM_ACPI_MMIO_PM_OFFSET 0x00000300
0087 #define EFCH_PM_ACPI_MMIO_WDT_OFFSET    0x00000b00
0088
0089 #define EFCH_PM_ACPI_MMIO_PM_ADDR   (EFCH_PM_ACPI_MMIO_ADDR +   \
0090                      EFCH_PM_ACPI_MMIO_PM_OFFSET)
0091 #define EFCH_PM_ACPI_MMIO_PM_SIZE   8
0092 #define AMD_ZEN_SMBUS_PCI_REV       0x51