drivers/watchdog/rza_wdt.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas RZ/A Series WDT Driver
0004  *
0005  * Copyright (C) 2017 Renesas Electronics America, Inc.
0006  * Copyright (C) 2017 Chris Brandt
0007  */
0008
0009 #include <linux/bitops.h>
0010 #include <linux/clk.h>
0011 #include <linux/delay.h>
0012 #include <linux/module.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_device.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/watchdog.h>
0017
0018 #define DEFAULT_TIMEOUT     30
0019
0020 /* Watchdog Timer Registers */
0021 #define WTCSR           0
0022 #define WTCSR_MAGIC     0xA500
0023 #define WTSCR_WT        BIT(6)
0024 #define WTSCR_TME       BIT(5)
0025 #define WTSCR_CKS(i)        (i)
0026
0027 #define WTCNT           2
0028 #define WTCNT_MAGIC     0x5A00
0029
0030 #define WRCSR           4
0031 #define WRCSR_MAGIC     0x5A00
0032 #define WRCSR_RSTE      BIT(6)
0033 #define WRCSR_CLEAR_WOVF    0xA500  /* special value */
0034
0035 /* The maximum CKS register setting value to get the longest timeout */
0036 #define CKS_3BIT        0x7
0037 #define CKS_4BIT        0xF
0038
0039 #define DIVIDER_3BIT        16384   /* Clock divider when CKS = 0x7 */
0040 #define DIVIDER_4BIT        4194304 /* Clock divider when CKS = 0xF */
0041
0042 struct rza_wdt {
0043     struct watchdog_device wdev;
0044     void __iomem *base;
0045     struct clk *clk;
0046     u8 count;
0047     u8 cks;
0048 };
0049
0050 static void rza_wdt_calc_timeout(struct rza_wdt *priv, int timeout)
0051 {
0052     unsigned long rate = clk_get_rate(priv->clk);
0053     unsigned int ticks;
0054
0055     if (priv->cks == CKS_4BIT) {
0056         ticks = DIV_ROUND_UP(timeout * rate, DIVIDER_4BIT);
0057
0058         /*
0059          * Since max_timeout was set in probe, we know that the timeout
0060          * value passed will never calculate to a tick value greater
0061          * than 256.
0062          */
0063         priv->count = 256 - ticks;
0064
0065     } else {
0066         /* Start timer with longest timeout */
0067         priv->count = 0;
0068     }
0069
0070     pr_debug("%s: timeout set to %u (WTCNT=%d)\n", __func__,
0071          timeout, priv->count);
0072 }
0073
0074 static int rza_wdt_start(struct watchdog_device *wdev)
0075 {
0076     struct rza_wdt *priv = watchdog_get_drvdata(wdev);
0077
0078     /* Stop timer */
0079     writew(WTCSR_MAGIC | 0, priv->base + WTCSR);
0080
0081     /* Must dummy read WRCSR:WOVF at least once before clearing */
0082     readb(priv->base + WRCSR);
0083     writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR);
0084
0085     rza_wdt_calc_timeout(priv, wdev->timeout);
0086
0087     writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR);
0088     writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT);
0089     writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME |
0090            WTSCR_CKS(priv->cks), priv->base + WTCSR);
0091
0092     return 0;
0093 }
0094
0095 static int rza_wdt_stop(struct watchdog_device *wdev)
0096 {
0097     struct rza_wdt *priv = watchdog_get_drvdata(wdev);
0098
0099     writew(WTCSR_MAGIC | 0, priv->base + WTCSR);
0100
0101     return 0;
0102 }
0103
0104 static int rza_wdt_ping(struct watchdog_device *wdev)
0105 {
0106     struct rza_wdt *priv = watchdog_get_drvdata(wdev);
0107
0108     writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT);
0109
0110     pr_debug("%s: timeout = %u\n", __func__, wdev->timeout);
0111
0112     return 0;
0113 }
0114
0115 static int rza_set_timeout(struct watchdog_device *wdev, unsigned int timeout)
0116 {
0117     wdev->timeout = timeout;
0118     rza_wdt_start(wdev);
0119     return 0;
0120 }
0121
0122 static int rza_wdt_restart(struct watchdog_device *wdev, unsigned long action,
0123                 void *data)
0124 {
0125     struct rza_wdt *priv = watchdog_get_drvdata(wdev);
0126
0127     /* Stop timer */
0128     writew(WTCSR_MAGIC | 0, priv->base + WTCSR);
0129
0130     /* Must dummy read WRCSR:WOVF at least once before clearing */
0131     readb(priv->base + WRCSR);
0132     writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR);
0133
0134     /*
0135      * Start timer with fastest clock source and only 1 clock left before
0136      * overflow with reset option enabled.
0137      */
0138     writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR);
0139     writew(WTCNT_MAGIC | 255, priv->base + WTCNT);
0140     writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME, priv->base + WTCSR);
0141
0142     /*
0143      * Actually make sure the above sequence hits hardware before sleeping.
0144      */
0145     wmb();
0146
0147     /* Wait for WDT overflow (reset) */
0148     udelay(20);
0149
0150     return 0;
0151 }
0152
0153 static const struct watchdog_info rza_wdt_ident = {
0154     .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
0155     .identity = "Renesas RZ/A WDT Watchdog",
0156 };
0157
0158 static const struct watchdog_ops rza_wdt_ops = {
0159     .owner = THIS_MODULE,
0160     .start = rza_wdt_start,
0161     .stop = rza_wdt_stop,
0162     .ping = rza_wdt_ping,
0163     .set_timeout = rza_set_timeout,
0164     .restart = rza_wdt_restart,
0165 };
0166
0167 static int rza_wdt_probe(struct platform_device *pdev)
0168 {
0169     struct device *dev = &pdev->dev;
0170     struct rza_wdt *priv;
0171     unsigned long rate;
0172     int ret;
0173
0174     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0175     if (!priv)
0176         return -ENOMEM;
0177
0178     priv->base = devm_platform_ioremap_resource(pdev, 0);
0179     if (IS_ERR(priv->base))
0180         return PTR_ERR(priv->base);
0181
0182     priv->clk = devm_clk_get(dev, NULL);
0183     if (IS_ERR(priv->clk))
0184         return PTR_ERR(priv->clk);
0185
0186     rate = clk_get_rate(priv->clk);
0187     if (rate < 16384) {
0188         dev_err(dev, "invalid clock rate (%ld)\n", rate);
0189         return -ENOENT;
0190     }
0191
0192     priv->wdev.info = &rza_wdt_ident;
0193     priv->wdev.ops = &rza_wdt_ops;
0194     priv->wdev.parent = dev;
0195
0196     priv->cks = (u8)(uintptr_t) of_device_get_match_data(dev);
0197     if (priv->cks == CKS_4BIT) {
0198         /* Assume slowest clock rate possible (CKS=0xF) */
0199         priv->wdev.max_timeout = (DIVIDER_4BIT * U8_MAX) / rate;
0200
0201     } else if (priv->cks == CKS_3BIT) {
0202         /* Assume slowest clock rate possible (CKS=7) */
0203         rate /= DIVIDER_3BIT;
0204
0205         /*
0206          * Since the max possible timeout of our 8-bit count
0207          * register is less than a second, we must use
0208          * max_hw_heartbeat_ms.
0209          */
0210         priv->wdev.max_hw_heartbeat_ms = (1000 * U8_MAX) / rate;
0211         dev_dbg(dev, "max hw timeout of %dms\n",
0212             priv->wdev.max_hw_heartbeat_ms);
0213     }
0214
0215     priv->wdev.min_timeout = 1;
0216     priv->wdev.timeout = DEFAULT_TIMEOUT;
0217
0218     watchdog_init_timeout(&priv->wdev, 0, dev);
0219     watchdog_set_drvdata(&priv->wdev, priv);
0220
0221     ret = devm_watchdog_register_device(dev, &priv->wdev);
0222     if (ret)
0223         dev_err(dev, "Cannot register watchdog device\n");
0224
0225     return ret;
0226 }
0227
0228 static const struct of_device_id rza_wdt_of_match[] = {
0229     { .compatible = "renesas,r7s9210-wdt",  .data = (void *)CKS_4BIT, },
0230     { .compatible = "renesas,rza-wdt",  .data = (void *)CKS_3BIT, },
0231     { /* sentinel */ }
0232 };
0233 MODULE_DEVICE_TABLE(of, rza_wdt_of_match);
0234
0235 static struct platform_driver rza_wdt_driver = {
0236     .probe = rza_wdt_probe,
0237     .driver = {
0238         .name = "rza_wdt",
0239         .of_match_table = rza_wdt_of_match,
0240     },
0241 };
0242
0243 module_platform_driver(rza_wdt_driver);
0244
0245 MODULE_DESCRIPTION("Renesas RZ/A WDT Driver");
0246 MODULE_AUTHOR("Chris Brandt <chris.brandt@renesas.com>");
0247 MODULE_LICENSE("GPL v2");