drivers/watchdog/rt2880_wdt.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Ralink RT288x/RT3xxx/MT76xx built-in hardware watchdog timer
0004  *
0005  * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
0006  * Copyright (C) 2013 John Crispin <john@phrozen.org>
0007  *
0008  * This driver was based on: drivers/watchdog/softdog.c
0009  */
0010
0011 #include <linux/clk.h>
0012 #include <linux/reset.h>
0013 #include <linux/module.h>
0014 #include <linux/kernel.h>
0015 #include <linux/watchdog.h>
0016 #include <linux/moduleparam.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/mod_devicetable.h>
0019
0020 #include <asm/mach-ralink/ralink_regs.h>
0021
0022 #define SYSC_RSTSTAT            0x38
0023 #define WDT_RST_CAUSE           BIT(1)
0024
0025 #define RALINK_WDT_TIMEOUT      30
0026 #define RALINK_WDT_PRESCALE     65536
0027
0028 #define TIMER_REG_TMR1LOAD      0x00
0029 #define TIMER_REG_TMR1CTL       0x08
0030
0031 #define TMRSTAT_TMR1RST         BIT(5)
0032
0033 #define TMR1CTL_ENABLE          BIT(7)
0034 #define TMR1CTL_MODE_SHIFT      4
0035 #define TMR1CTL_MODE_MASK       0x3
0036 #define TMR1CTL_MODE_FREE_RUNNING   0x0
0037 #define TMR1CTL_MODE_PERIODIC       0x1
0038 #define TMR1CTL_MODE_TIMEOUT        0x2
0039 #define TMR1CTL_MODE_WDT        0x3
0040 #define TMR1CTL_PRESCALE_MASK       0xf
0041 #define TMR1CTL_PRESCALE_65536      0xf
0042
0043 static struct clk *rt288x_wdt_clk;
0044 static unsigned long rt288x_wdt_freq;
0045 static void __iomem *rt288x_wdt_base;
0046 static struct reset_control *rt288x_wdt_reset;
0047
0048 static bool nowayout = WATCHDOG_NOWAYOUT;
0049 module_param(nowayout, bool, 0);
0050 MODULE_PARM_DESC(nowayout,
0051         "Watchdog cannot be stopped once started (default="
0052         __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
0053
0054 static inline void rt_wdt_w32(unsigned reg, u32 val)
0055 {
0056     iowrite32(val, rt288x_wdt_base + reg);
0057 }
0058
0059 static inline u32 rt_wdt_r32(unsigned reg)
0060 {
0061     return ioread32(rt288x_wdt_base + reg);
0062 }
0063
0064 static int rt288x_wdt_ping(struct watchdog_device *w)
0065 {
0066     rt_wdt_w32(TIMER_REG_TMR1LOAD, w->timeout * rt288x_wdt_freq);
0067
0068     return 0;
0069 }
0070
0071 static int rt288x_wdt_start(struct watchdog_device *w)
0072 {
0073     u32 t;
0074
0075     t = rt_wdt_r32(TIMER_REG_TMR1CTL);
0076     t &= ~(TMR1CTL_MODE_MASK << TMR1CTL_MODE_SHIFT |
0077         TMR1CTL_PRESCALE_MASK);
0078     t |= (TMR1CTL_MODE_WDT << TMR1CTL_MODE_SHIFT |
0079         TMR1CTL_PRESCALE_65536);
0080     rt_wdt_w32(TIMER_REG_TMR1CTL, t);
0081
0082     rt288x_wdt_ping(w);
0083
0084     t = rt_wdt_r32(TIMER_REG_TMR1CTL);
0085     t |= TMR1CTL_ENABLE;
0086     rt_wdt_w32(TIMER_REG_TMR1CTL, t);
0087
0088     return 0;
0089 }
0090
0091 static int rt288x_wdt_stop(struct watchdog_device *w)
0092 {
0093     u32 t;
0094
0095     rt288x_wdt_ping(w);
0096
0097     t = rt_wdt_r32(TIMER_REG_TMR1CTL);
0098     t &= ~TMR1CTL_ENABLE;
0099     rt_wdt_w32(TIMER_REG_TMR1CTL, t);
0100
0101     return 0;
0102 }
0103
0104 static int rt288x_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
0105 {
0106     w->timeout = t;
0107     rt288x_wdt_ping(w);
0108
0109     return 0;
0110 }
0111
0112 static int rt288x_wdt_bootcause(void)
0113 {
0114     if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
0115         return WDIOF_CARDRESET;
0116
0117     return 0;
0118 }
0119
0120 static const struct watchdog_info rt288x_wdt_info = {
0121     .identity = "Ralink Watchdog",
0122     .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
0123 };
0124
0125 static const struct watchdog_ops rt288x_wdt_ops = {
0126     .owner = THIS_MODULE,
0127     .start = rt288x_wdt_start,
0128     .stop = rt288x_wdt_stop,
0129     .ping = rt288x_wdt_ping,
0130     .set_timeout = rt288x_wdt_set_timeout,
0131 };
0132
0133 static struct watchdog_device rt288x_wdt_dev = {
0134     .info = &rt288x_wdt_info,
0135     .ops = &rt288x_wdt_ops,
0136     .min_timeout = 1,
0137 };
0138
0139 static int rt288x_wdt_probe(struct platform_device *pdev)
0140 {
0141     struct device *dev = &pdev->dev;
0142     int ret;
0143
0144     rt288x_wdt_base = devm_platform_ioremap_resource(pdev, 0);
0145     if (IS_ERR(rt288x_wdt_base))
0146         return PTR_ERR(rt288x_wdt_base);
0147
0148     rt288x_wdt_clk = devm_clk_get(dev, NULL);
0149     if (IS_ERR(rt288x_wdt_clk))
0150         return PTR_ERR(rt288x_wdt_clk);
0151
0152     rt288x_wdt_reset = devm_reset_control_get_exclusive(dev, NULL);
0153     if (!IS_ERR(rt288x_wdt_reset))
0154         reset_control_deassert(rt288x_wdt_reset);
0155
0156     rt288x_wdt_freq = clk_get_rate(rt288x_wdt_clk) / RALINK_WDT_PRESCALE;
0157
0158     rt288x_wdt_dev.bootstatus = rt288x_wdt_bootcause();
0159     rt288x_wdt_dev.max_timeout = (0xfffful / rt288x_wdt_freq);
0160     rt288x_wdt_dev.parent = dev;
0161
0162     watchdog_init_timeout(&rt288x_wdt_dev, rt288x_wdt_dev.max_timeout,
0163                   dev);
0164     watchdog_set_nowayout(&rt288x_wdt_dev, nowayout);
0165
0166     watchdog_stop_on_reboot(&rt288x_wdt_dev);
0167     ret = devm_watchdog_register_device(dev, &rt288x_wdt_dev);
0168     if (!ret)
0169         dev_info(dev, "Initialized\n");
0170
0171     return 0;
0172 }
0173
0174 static const struct of_device_id rt288x_wdt_match[] = {
0175     { .compatible = "ralink,rt2880-wdt" },
0176     {},
0177 };
0178 MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
0179
0180 static struct platform_driver rt288x_wdt_driver = {
0181     .probe      = rt288x_wdt_probe,
0182     .driver     = {
0183         .name       = KBUILD_MODNAME,
0184         .of_match_table = rt288x_wdt_match,
0185     },
0186 };
0187
0188 module_platform_driver(rt288x_wdt_driver);
0189
0190 MODULE_DESCRIPTION("MediaTek/Ralink RT288x/RT3xxx hardware watchdog driver");
0191 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org");
0192 MODULE_LICENSE("GPL v2");