drivers/watchdog/renesas_wdt.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Watchdog driver for Renesas WDT watchdog
0004  *
0005  * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
0006  * Copyright (C) 2015-17 Renesas Electronics Corporation
0007  */
0008 #include <linux/bitops.h>
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/io.h>
0012 #include <linux/iopoll.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/of.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/smp.h>
0019 #include <linux/sys_soc.h>
0020 #include <linux/watchdog.h>
0021
0022 #define RWTCNT      0
0023 #define RWTCSRA     4
0024 #define RWTCSRA_WOVF    BIT(4)
0025 #define RWTCSRA_WRFLG   BIT(5)
0026 #define RWTCSRA_TME BIT(7)
0027 #define RWTCSRB     8
0028
0029 #define RWDT_DEFAULT_TIMEOUT 60U
0030
0031 /*
0032  * In probe, clk_rate is checked to be not more than 16 bit * biggest clock
0033  * divider (12 bits). d is only a factor to fully utilize the WDT counter and
0034  * will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
0035  */
0036 #define MUL_BY_CLKS_PER_SEC(p, d) \
0037     DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
0038
0039 /* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
0040 #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
0041
0042 static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 };
0043
0044 static bool nowayout = WATCHDOG_NOWAYOUT;
0045 module_param(nowayout, bool, 0);
0046 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
0047                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
0048
0049 struct rwdt_priv {
0050     void __iomem *base;
0051     struct watchdog_device wdev;
0052     unsigned long clk_rate;
0053     u8 cks;
0054     struct clk *clk;
0055 };
0056
0057 static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg)
0058 {
0059     if (reg == RWTCNT)
0060         val |= 0x5a5a0000;
0061     else
0062         val |= 0xa5a5a500;
0063
0064     writel_relaxed(val, priv->base + reg);
0065 }
0066
0067 static int rwdt_init_timeout(struct watchdog_device *wdev)
0068 {
0069     struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
0070
0071     rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT);
0072
0073     return 0;
0074 }
0075
0076 static void rwdt_wait_cycles(struct rwdt_priv *priv, unsigned int cycles)
0077 {
0078     unsigned int delay;
0079
0080     delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate);
0081
0082     usleep_range(delay, 2 * delay);
0083 }
0084
0085 static int rwdt_start(struct watchdog_device *wdev)
0086 {
0087     struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
0088     u8 val;
0089
0090     pm_runtime_get_sync(wdev->parent);
0091
0092     /* Stop the timer before we modify any register */
0093     val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
0094     rwdt_write(priv, val, RWTCSRA);
0095     /* Delay 2 cycles before setting watchdog counter */
0096     rwdt_wait_cycles(priv, 2);
0097
0098     rwdt_init_timeout(wdev);
0099     rwdt_write(priv, priv->cks, RWTCSRA);
0100     rwdt_write(priv, 0, RWTCSRB);
0101
0102     while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
0103         cpu_relax();
0104
0105     rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA);
0106
0107     return 0;
0108 }
0109
0110 static int rwdt_stop(struct watchdog_device *wdev)
0111 {
0112     struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
0113
0114     rwdt_write(priv, priv->cks, RWTCSRA);
0115     /* Delay 3 cycles before disabling module clock */
0116     rwdt_wait_cycles(priv, 3);
0117     pm_runtime_put(wdev->parent);
0118
0119     return 0;
0120 }
0121
0122 static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev)
0123 {
0124     struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
0125     u16 val = readw_relaxed(priv->base + RWTCNT);
0126
0127     return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
0128 }
0129
0130 /* needs to be atomic - no RPM, no usleep_range, no scheduling! */
0131 static int rwdt_restart(struct watchdog_device *wdev, unsigned long action,
0132             void *data)
0133 {
0134     struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
0135     u8 val;
0136
0137     clk_prepare_enable(priv->clk);
0138
0139     /* Stop the timer before we modify any register */
0140     val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
0141     rwdt_write(priv, val, RWTCSRA);
0142     /* Delay 2 cycles before setting watchdog counter */
0143     udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate));
0144
0145     rwdt_write(priv, 0xffff, RWTCNT);
0146     /* smallest divider to reboot soon */
0147     rwdt_write(priv, 0, RWTCSRA);
0148
0149     readb_poll_timeout_atomic(priv->base + RWTCSRA, val,
0150                   !(val & RWTCSRA_WRFLG), 1, 100);
0151
0152     rwdt_write(priv, RWTCSRA_TME, RWTCSRA);
0153
0154     /* wait 2 cycles, so watchdog will trigger */
0155     udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate));
0156
0157     return 0;
0158 }
0159
0160 static const struct watchdog_info rwdt_ident = {
0161     .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
0162         WDIOF_CARDRESET,
0163     .identity = "Renesas WDT Watchdog",
0164 };
0165
0166 static const struct watchdog_ops rwdt_ops = {
0167     .owner = THIS_MODULE,
0168     .start = rwdt_start,
0169     .stop = rwdt_stop,
0170     .ping = rwdt_init_timeout,
0171     .get_timeleft = rwdt_get_timeleft,
0172     .restart = rwdt_restart,
0173 };
0174
0175 #if defined(CONFIG_ARCH_RCAR_GEN2) && defined(CONFIG_SMP)
0176 /*
0177  * Watchdog-reset integration is broken on early revisions of R-Car Gen2 SoCs
0178  */
0179 static const struct soc_device_attribute rwdt_quirks_match[] = {
0180     {
0181         .soc_id = "r8a7790",
0182         .revision = "ES1.*",
0183         .data = (void *)1,  /* needs single CPU */
0184     }, {
0185         .soc_id = "r8a7791",
0186         .revision = "ES1.*",
0187         .data = (void *)1,  /* needs single CPU */
0188     }, {
0189         .soc_id = "r8a7792",
0190         .data = (void *)0,  /* needs SMP disabled */
0191     },
0192     { /* sentinel */ }
0193 };
0194
0195 static bool rwdt_blacklisted(struct device *dev)
0196 {
0197     const struct soc_device_attribute *attr;
0198
0199     attr = soc_device_match(rwdt_quirks_match);
0200     if (attr && setup_max_cpus > (uintptr_t)attr->data) {
0201         dev_info(dev, "Watchdog blacklisted on %s %s\n", attr->soc_id,
0202              attr->revision);
0203         return true;
0204     }
0205
0206     return false;
0207 }
0208 #else /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */
0209 static inline bool rwdt_blacklisted(struct device *dev) { return false; }
0210 #endif /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */
0211
0212 static int rwdt_probe(struct platform_device *pdev)
0213 {
0214     struct device *dev = &pdev->dev;
0215     struct rwdt_priv *priv;
0216     unsigned long clks_per_sec;
0217     int ret, i;
0218     u8 csra;
0219
0220     if (rwdt_blacklisted(dev))
0221         return -ENODEV;
0222
0223     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0224     if (!priv)
0225         return -ENOMEM;
0226
0227     priv->base = devm_platform_ioremap_resource(pdev, 0);
0228     if (IS_ERR(priv->base))
0229         return PTR_ERR(priv->base);
0230
0231     priv->clk = devm_clk_get(dev, NULL);
0232     if (IS_ERR(priv->clk))
0233         return PTR_ERR(priv->clk);
0234
0235     pm_runtime_enable(dev);
0236     pm_runtime_get_sync(dev);
0237     priv->clk_rate = clk_get_rate(priv->clk);
0238     csra = readb_relaxed(priv->base + RWTCSRA);
0239     priv->wdev.bootstatus = csra & RWTCSRA_WOVF ? WDIOF_CARDRESET : 0;
0240     pm_runtime_put(dev);
0241
0242     if (!priv->clk_rate) {
0243         ret = -ENOENT;
0244         goto out_pm_disable;
0245     }
0246
0247     for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
0248         clks_per_sec = priv->clk_rate / clk_divs[i];
0249         if (clks_per_sec && clks_per_sec < 65536) {
0250             priv->cks = i;
0251             break;
0252         }
0253     }
0254
0255     if (i < 0) {
0256         dev_err(dev, "Can't find suitable clock divider\n");
0257         ret = -ERANGE;
0258         goto out_pm_disable;
0259     }
0260
0261     priv->wdev.info = &rwdt_ident;
0262     priv->wdev.ops = &rwdt_ops;
0263     priv->wdev.parent = dev;
0264     priv->wdev.min_timeout = 1;
0265     priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
0266     priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);
0267
0268     platform_set_drvdata(pdev, priv);
0269     watchdog_set_drvdata(&priv->wdev, priv);
0270     watchdog_set_nowayout(&priv->wdev, nowayout);
0271     watchdog_set_restart_priority(&priv->wdev, 0);
0272     watchdog_stop_on_unregister(&priv->wdev);
0273
0274     /* This overrides the default timeout only if DT configuration was found */
0275     watchdog_init_timeout(&priv->wdev, 0, dev);
0276
0277     /* Check if FW enabled the watchdog */
0278     if (csra & RWTCSRA_TME) {
0279         /* Ensure properly initialized dividers */
0280         rwdt_start(&priv->wdev);
0281         set_bit(WDOG_HW_RUNNING, &priv->wdev.status);
0282     }
0283
0284     ret = watchdog_register_device(&priv->wdev);
0285     if (ret < 0)
0286         goto out_pm_disable;
0287
0288     return 0;
0289
0290  out_pm_disable:
0291     pm_runtime_disable(dev);
0292     return ret;
0293 }
0294
0295 static int rwdt_remove(struct platform_device *pdev)
0296 {
0297     struct rwdt_priv *priv = platform_get_drvdata(pdev);
0298
0299     watchdog_unregister_device(&priv->wdev);
0300     pm_runtime_disable(&pdev->dev);
0301
0302     return 0;
0303 }
0304
0305 static int __maybe_unused rwdt_suspend(struct device *dev)
0306 {
0307     struct rwdt_priv *priv = dev_get_drvdata(dev);
0308
0309     if (watchdog_active(&priv->wdev))
0310         rwdt_stop(&priv->wdev);
0311
0312     return 0;
0313 }
0314
0315 static int __maybe_unused rwdt_resume(struct device *dev)
0316 {
0317     struct rwdt_priv *priv = dev_get_drvdata(dev);
0318
0319     if (watchdog_active(&priv->wdev))
0320         rwdt_start(&priv->wdev);
0321
0322     return 0;
0323 }
0324
0325 static SIMPLE_DEV_PM_OPS(rwdt_pm_ops, rwdt_suspend, rwdt_resume);
0326
0327 static const struct of_device_id rwdt_ids[] = {
0328     { .compatible = "renesas,rcar-gen2-wdt", },
0329     { .compatible = "renesas,rcar-gen3-wdt", },
0330     { .compatible = "renesas,rcar-gen4-wdt", },
0331     { /* sentinel */ }
0332 };
0333 MODULE_DEVICE_TABLE(of, rwdt_ids);
0334
0335 static struct platform_driver rwdt_driver = {
0336     .driver = {
0337         .name = "renesas_wdt",
0338         .of_match_table = rwdt_ids,
0339         .pm = &rwdt_pm_ops,
0340     },
0341     .probe = rwdt_probe,
0342     .remove = rwdt_remove,
0343 };
0344 module_platform_driver(rwdt_driver);
0345
0346 MODULE_DESCRIPTION("Renesas WDT Watchdog Driver");
0347 MODULE_LICENSE("GPL v2");
0348 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");