drivers/watchdog/qcom-wdt.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
0003  */
0004 #include <linux/bits.h>
0005 #include <linux/clk.h>
0006 #include <linux/delay.h>
0007 #include <linux/interrupt.h>
0008 #include <linux/io.h>
0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/watchdog.h>
0014 #include <linux/of_device.h>
0015
0016 enum wdt_reg {
0017     WDT_RST,
0018     WDT_EN,
0019     WDT_STS,
0020     WDT_BARK_TIME,
0021     WDT_BITE_TIME,
0022 };
0023
0024 #define QCOM_WDT_ENABLE     BIT(0)
0025
0026 static const u32 reg_offset_data_apcs_tmr[] = {
0027     [WDT_RST] = 0x38,
0028     [WDT_EN] = 0x40,
0029     [WDT_STS] = 0x44,
0030     [WDT_BARK_TIME] = 0x4C,
0031     [WDT_BITE_TIME] = 0x5C,
0032 };
0033
0034 static const u32 reg_offset_data_kpss[] = {
0035     [WDT_RST] = 0x4,
0036     [WDT_EN] = 0x8,
0037     [WDT_STS] = 0xC,
0038     [WDT_BARK_TIME] = 0x10,
0039     [WDT_BITE_TIME] = 0x14,
0040 };
0041
0042 struct qcom_wdt_match_data {
0043     const u32 *offset;
0044     bool pretimeout;
0045 };
0046
0047 struct qcom_wdt {
0048     struct watchdog_device  wdd;
0049     unsigned long       rate;
0050     void __iomem        *base;
0051     const u32       *layout;
0052 };
0053
0054 static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
0055 {
0056     return wdt->base + wdt->layout[reg];
0057 }
0058
0059 static inline
0060 struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
0061 {
0062     return container_of(wdd, struct qcom_wdt, wdd);
0063 }
0064
0065 static irqreturn_t qcom_wdt_isr(int irq, void *arg)
0066 {
0067     struct watchdog_device *wdd = arg;
0068
0069     watchdog_notify_pretimeout(wdd);
0070
0071     return IRQ_HANDLED;
0072 }
0073
0074 static int qcom_wdt_start(struct watchdog_device *wdd)
0075 {
0076     struct qcom_wdt *wdt = to_qcom_wdt(wdd);
0077     unsigned int bark = wdd->timeout - wdd->pretimeout;
0078
0079     writel(0, wdt_addr(wdt, WDT_EN));
0080     writel(1, wdt_addr(wdt, WDT_RST));
0081     writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
0082     writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
0083     writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
0084     return 0;
0085 }
0086
0087 static int qcom_wdt_stop(struct watchdog_device *wdd)
0088 {
0089     struct qcom_wdt *wdt = to_qcom_wdt(wdd);
0090
0091     writel(0, wdt_addr(wdt, WDT_EN));
0092     return 0;
0093 }
0094
0095 static int qcom_wdt_ping(struct watchdog_device *wdd)
0096 {
0097     struct qcom_wdt *wdt = to_qcom_wdt(wdd);
0098
0099     writel(1, wdt_addr(wdt, WDT_RST));
0100     return 0;
0101 }
0102
0103 static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
0104                 unsigned int timeout)
0105 {
0106     wdd->timeout = timeout;
0107     return qcom_wdt_start(wdd);
0108 }
0109
0110 static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd,
0111                    unsigned int timeout)
0112 {
0113     wdd->pretimeout = timeout;
0114     return qcom_wdt_start(wdd);
0115 }
0116
0117 static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
0118                 void *data)
0119 {
0120     struct qcom_wdt *wdt = to_qcom_wdt(wdd);
0121     u32 timeout;
0122
0123     /*
0124      * Trigger watchdog bite:
0125      *    Setup BITE_TIME to be 128ms, and enable WDT.
0126      */
0127     timeout = 128 * wdt->rate / 1000;
0128
0129     writel(0, wdt_addr(wdt, WDT_EN));
0130     writel(1, wdt_addr(wdt, WDT_RST));
0131     writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
0132     writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
0133     writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
0134
0135     /*
0136      * Actually make sure the above sequence hits hardware before sleeping.
0137      */
0138     wmb();
0139
0140     mdelay(150);
0141     return 0;
0142 }
0143
0144 static int qcom_wdt_is_running(struct watchdog_device *wdd)
0145 {
0146     struct qcom_wdt *wdt = to_qcom_wdt(wdd);
0147
0148     return (readl(wdt_addr(wdt, WDT_EN)) & QCOM_WDT_ENABLE);
0149 }
0150
0151 static const struct watchdog_ops qcom_wdt_ops = {
0152     .start      = qcom_wdt_start,
0153     .stop       = qcom_wdt_stop,
0154     .ping       = qcom_wdt_ping,
0155     .set_timeout    = qcom_wdt_set_timeout,
0156     .set_pretimeout = qcom_wdt_set_pretimeout,
0157     .restart        = qcom_wdt_restart,
0158     .owner      = THIS_MODULE,
0159 };
0160
0161 static const struct watchdog_info qcom_wdt_info = {
0162     .options    = WDIOF_KEEPALIVEPING
0163             | WDIOF_MAGICCLOSE
0164             | WDIOF_SETTIMEOUT
0165             | WDIOF_CARDRESET,
0166     .identity   = KBUILD_MODNAME,
0167 };
0168
0169 static const struct watchdog_info qcom_wdt_pt_info = {
0170     .options    = WDIOF_KEEPALIVEPING
0171             | WDIOF_MAGICCLOSE
0172             | WDIOF_SETTIMEOUT
0173             | WDIOF_PRETIMEOUT
0174             | WDIOF_CARDRESET,
0175     .identity   = KBUILD_MODNAME,
0176 };
0177
0178 static void qcom_clk_disable_unprepare(void *data)
0179 {
0180     clk_disable_unprepare(data);
0181 }
0182
0183 static const struct qcom_wdt_match_data match_data_apcs_tmr = {
0184     .offset = reg_offset_data_apcs_tmr,
0185     .pretimeout = false,
0186 };
0187
0188 static const struct qcom_wdt_match_data match_data_kpss = {
0189     .offset = reg_offset_data_kpss,
0190     .pretimeout = true,
0191 };
0192
0193 static int qcom_wdt_probe(struct platform_device *pdev)
0194 {
0195     struct device *dev = &pdev->dev;
0196     struct qcom_wdt *wdt;
0197     struct resource *res;
0198     struct device_node *np = dev->of_node;
0199     const struct qcom_wdt_match_data *data;
0200     u32 percpu_offset;
0201     int irq, ret;
0202     struct clk *clk;
0203
0204     data = of_device_get_match_data(dev);
0205     if (!data) {
0206         dev_err(dev, "Unsupported QCOM WDT module\n");
0207         return -ENODEV;
0208     }
0209
0210     wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
0211     if (!wdt)
0212         return -ENOMEM;
0213
0214     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0215     if (!res)
0216         return -ENOMEM;
0217
0218     /* We use CPU0's DGT for the watchdog */
0219     if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
0220         percpu_offset = 0;
0221
0222     res->start += percpu_offset;
0223     res->end += percpu_offset;
0224
0225     wdt->base = devm_ioremap_resource(dev, res);
0226     if (IS_ERR(wdt->base))
0227         return PTR_ERR(wdt->base);
0228
0229     clk = devm_clk_get(dev, NULL);
0230     if (IS_ERR(clk)) {
0231         dev_err(dev, "failed to get input clock\n");
0232         return PTR_ERR(clk);
0233     }
0234
0235     ret = clk_prepare_enable(clk);
0236     if (ret) {
0237         dev_err(dev, "failed to setup clock\n");
0238         return ret;
0239     }
0240     ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare, clk);
0241     if (ret)
0242         return ret;
0243
0244     /*
0245      * We use the clock rate to calculate the max timeout, so ensure it's
0246      * not zero to avoid a divide-by-zero exception.
0247      *
0248      * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
0249      * that it would bite before a second elapses it's usefulness is
0250      * limited.  Bail if this is the case.
0251      */
0252     wdt->rate = clk_get_rate(clk);
0253     if (wdt->rate == 0 ||
0254         wdt->rate > 0x10000000U) {
0255         dev_err(dev, "invalid clock rate\n");
0256         return -EINVAL;
0257     }
0258
0259     /* check if there is pretimeout support */
0260     irq = platform_get_irq_optional(pdev, 0);
0261     if (data->pretimeout && irq > 0) {
0262         ret = devm_request_irq(dev, irq, qcom_wdt_isr, 0,
0263                        "wdt_bark", &wdt->wdd);
0264         if (ret)
0265             return ret;
0266
0267         wdt->wdd.info = &qcom_wdt_pt_info;
0268         wdt->wdd.pretimeout = 1;
0269     } else {
0270         if (irq == -EPROBE_DEFER)
0271             return -EPROBE_DEFER;
0272
0273         wdt->wdd.info = &qcom_wdt_info;
0274     }
0275
0276     wdt->wdd.ops = &qcom_wdt_ops;
0277     wdt->wdd.min_timeout = 1;
0278     wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
0279     wdt->wdd.parent = dev;
0280     wdt->layout = data->offset;
0281
0282     if (readl(wdt_addr(wdt, WDT_STS)) & 1)
0283         wdt->wdd.bootstatus = WDIOF_CARDRESET;
0284
0285     /*
0286      * If 'timeout-sec' unspecified in devicetree, assume a 30 second
0287      * default, unless the max timeout is less than 30 seconds, then use
0288      * the max instead.
0289      */
0290     wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
0291     watchdog_init_timeout(&wdt->wdd, 0, dev);
0292
0293     /*
0294      * If WDT is already running, call WDT start which
0295      * will stop the WDT, set timeouts as bootloader
0296      * might use different ones and set running bit
0297      * to inform the WDT subsystem to ping the WDT
0298      */
0299     if (qcom_wdt_is_running(&wdt->wdd)) {
0300         qcom_wdt_start(&wdt->wdd);
0301         set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
0302     }
0303
0304     ret = devm_watchdog_register_device(dev, &wdt->wdd);
0305     if (ret)
0306         return ret;
0307
0308     platform_set_drvdata(pdev, wdt);
0309     return 0;
0310 }
0311
0312 static int __maybe_unused qcom_wdt_suspend(struct device *dev)
0313 {
0314     struct qcom_wdt *wdt = dev_get_drvdata(dev);
0315
0316     if (watchdog_active(&wdt->wdd))
0317         qcom_wdt_stop(&wdt->wdd);
0318
0319     return 0;
0320 }
0321
0322 static int __maybe_unused qcom_wdt_resume(struct device *dev)
0323 {
0324     struct qcom_wdt *wdt = dev_get_drvdata(dev);
0325
0326     if (watchdog_active(&wdt->wdd))
0327         qcom_wdt_start(&wdt->wdd);
0328
0329     return 0;
0330 }
0331
0332 static const struct dev_pm_ops qcom_wdt_pm_ops = {
0333     SET_LATE_SYSTEM_SLEEP_PM_OPS(qcom_wdt_suspend, qcom_wdt_resume)
0334 };
0335
0336 static const struct of_device_id qcom_wdt_of_table[] = {
0337     { .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr },
0338     { .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr },
0339     { .compatible = "qcom,kpss-wdt", .data = &match_data_kpss },
0340     { },
0341 };
0342 MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
0343
0344 static struct platform_driver qcom_watchdog_driver = {
0345     .probe  = qcom_wdt_probe,
0346     .driver = {
0347         .name       = KBUILD_MODNAME,
0348         .of_match_table = qcom_wdt_of_table,
0349         .pm     = &qcom_wdt_pm_ops,
0350     },
0351 };
0352 module_platform_driver(qcom_watchdog_driver);
0353
0354 MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
0355 MODULE_LICENSE("GPL v2");