drivers/watchdog/pnx4008_wdt.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * drivers/char/watchdog/pnx4008_wdt.c
0004  *
0005  * Watchdog driver for PNX4008 board
0006  *
0007  * Authors: Dmitry Chigirev <source@mvista.com>,
0008  *      Vitaly Wool <vitalywool@gmail.com>
0009  * Based on sa1100 driver,
0010  * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
0011  *
0012  * 2005-2006 (c) MontaVista Software, Inc.
0013  *
0014  * (C) 2012 Wolfram Sang, Pengutronix
0015  */
0016
0017 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0018
0019 #include <linux/module.h>
0020 #include <linux/moduleparam.h>
0021 #include <linux/types.h>
0022 #include <linux/kernel.h>
0023 #include <linux/watchdog.h>
0024 #include <linux/platform_device.h>
0025 #include <linux/clk.h>
0026 #include <linux/spinlock.h>
0027 #include <linux/io.h>
0028 #include <linux/slab.h>
0029 #include <linux/err.h>
0030 #include <linux/of.h>
0031 #include <linux/delay.h>
0032 #include <linux/reboot.h>
0033
0034 /* WatchDog Timer - Chapter 23 Page 207 */
0035
0036 #define DEFAULT_HEARTBEAT 19
0037 #define MAX_HEARTBEAT     60
0038
0039 /* Watchdog timer register set definition */
0040 #define WDTIM_INT(p)     ((p) + 0x0)
0041 #define WDTIM_CTRL(p)    ((p) + 0x4)
0042 #define WDTIM_COUNTER(p) ((p) + 0x8)
0043 #define WDTIM_MCTRL(p)   ((p) + 0xC)
0044 #define WDTIM_MATCH0(p)  ((p) + 0x10)
0045 #define WDTIM_EMR(p)     ((p) + 0x14)
0046 #define WDTIM_PULSE(p)   ((p) + 0x18)
0047 #define WDTIM_RES(p)     ((p) + 0x1C)
0048
0049 /* WDTIM_INT bit definitions */
0050 #define MATCH_INT      1
0051
0052 /* WDTIM_CTRL bit definitions */
0053 #define COUNT_ENAB     1
0054 #define RESET_COUNT    (1 << 1)
0055 #define DEBUG_EN       (1 << 2)
0056
0057 /* WDTIM_MCTRL bit definitions */
0058 #define MR0_INT        1
0059 #undef  RESET_COUNT0
0060 #define RESET_COUNT0   (1 << 2)
0061 #define STOP_COUNT0    (1 << 2)
0062 #define M_RES1         (1 << 3)
0063 #define M_RES2         (1 << 4)
0064 #define RESFRC1        (1 << 5)
0065 #define RESFRC2        (1 << 6)
0066
0067 /* WDTIM_EMR bit definitions */
0068 #define EXT_MATCH0      1
0069 #define MATCH_OUTPUT_HIGH (2 << 4)  /*a MATCH_CTRL setting */
0070
0071 /* WDTIM_RES bit definitions */
0072 #define WDOG_RESET      1   /* read only */
0073
0074 #define WDOG_COUNTER_RATE 13000000  /*the counter clock is 13 MHz fixed */
0075
0076 static bool nowayout = WATCHDOG_NOWAYOUT;
0077 static unsigned int heartbeat;
0078
0079 static DEFINE_SPINLOCK(io_lock);
0080 static void __iomem *wdt_base;
0081 static struct clk   *wdt_clk;
0082
0083 static int pnx4008_wdt_start(struct watchdog_device *wdd)
0084 {
0085     spin_lock(&io_lock);
0086
0087     /* stop counter, initiate counter reset */
0088     writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
0089     /*wait for reset to complete. 100% guarantee event */
0090     while (readl(WDTIM_COUNTER(wdt_base)))
0091         cpu_relax();
0092     /* internal and external reset, stop after that */
0093     writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base));
0094     /* configure match output */
0095     writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
0096     /* clear interrupt, just in case */
0097     writel(MATCH_INT, WDTIM_INT(wdt_base));
0098     /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
0099     writel(0xFFFF, WDTIM_PULSE(wdt_base));
0100     writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
0101     /*enable counter, stop when debugger active */
0102     writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));
0103
0104     spin_unlock(&io_lock);
0105     return 0;
0106 }
0107
0108 static int pnx4008_wdt_stop(struct watchdog_device *wdd)
0109 {
0110     spin_lock(&io_lock);
0111
0112     writel(0, WDTIM_CTRL(wdt_base));    /*stop counter */
0113
0114     spin_unlock(&io_lock);
0115     return 0;
0116 }
0117
0118 static int pnx4008_wdt_set_timeout(struct watchdog_device *wdd,
0119                     unsigned int new_timeout)
0120 {
0121     wdd->timeout = new_timeout;
0122     return 0;
0123 }
0124
0125 static int pnx4008_restart_handler(struct watchdog_device *wdd,
0126                    unsigned long mode, void *cmd)
0127 {
0128     const char *boot_cmd = cmd;
0129
0130     /*
0131      * Verify if a "cmd" passed from the userspace program rebooting
0132      * the system; if available, handle it.
0133      * - For details, see the 'reboot' syscall in kernel/reboot.c
0134      * - If the received "cmd" is not supported, use the default mode.
0135      */
0136     if (boot_cmd) {
0137         if (boot_cmd[0] == 'h')
0138             mode = REBOOT_HARD;
0139         else if (boot_cmd[0] == 's')
0140             mode = REBOOT_SOFT;
0141     }
0142
0143     if (mode == REBOOT_SOFT) {
0144         /* Force match output active */
0145         writel(EXT_MATCH0, WDTIM_EMR(wdt_base));
0146         /* Internal reset on match output (RESOUT_N not asserted) */
0147         writel(M_RES1, WDTIM_MCTRL(wdt_base));
0148     } else {
0149         /* Instant assert of RESETOUT_N with pulse length 1mS */
0150         writel(13000, WDTIM_PULSE(wdt_base));
0151         writel(M_RES2 | RESFRC1 | RESFRC2, WDTIM_MCTRL(wdt_base));
0152     }
0153
0154     /* Wait for watchdog to reset system */
0155     mdelay(1000);
0156
0157     return NOTIFY_DONE;
0158 }
0159
0160 static const struct watchdog_info pnx4008_wdt_ident = {
0161     .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
0162         WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
0163     .identity = "PNX4008 Watchdog",
0164 };
0165
0166 static const struct watchdog_ops pnx4008_wdt_ops = {
0167     .owner = THIS_MODULE,
0168     .start = pnx4008_wdt_start,
0169     .stop = pnx4008_wdt_stop,
0170     .set_timeout = pnx4008_wdt_set_timeout,
0171     .restart = pnx4008_restart_handler,
0172 };
0173
0174 static struct watchdog_device pnx4008_wdd = {
0175     .info = &pnx4008_wdt_ident,
0176     .ops = &pnx4008_wdt_ops,
0177     .timeout = DEFAULT_HEARTBEAT,
0178     .min_timeout = 1,
0179     .max_timeout = MAX_HEARTBEAT,
0180 };
0181
0182 static void pnx4008_clk_disable_unprepare(void *data)
0183 {
0184     clk_disable_unprepare(data);
0185 }
0186
0187 static int pnx4008_wdt_probe(struct platform_device *pdev)
0188 {
0189     struct device *dev = &pdev->dev;
0190     int ret = 0;
0191
0192     watchdog_init_timeout(&pnx4008_wdd, heartbeat, dev);
0193
0194     wdt_base = devm_platform_ioremap_resource(pdev, 0);
0195     if (IS_ERR(wdt_base))
0196         return PTR_ERR(wdt_base);
0197
0198     wdt_clk = devm_clk_get(dev, NULL);
0199     if (IS_ERR(wdt_clk))
0200         return PTR_ERR(wdt_clk);
0201
0202     ret = clk_prepare_enable(wdt_clk);
0203     if (ret)
0204         return ret;
0205     ret = devm_add_action_or_reset(dev, pnx4008_clk_disable_unprepare,
0206                        wdt_clk);
0207     if (ret)
0208         return ret;
0209
0210     pnx4008_wdd.bootstatus = (readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
0211             WDIOF_CARDRESET : 0;
0212     pnx4008_wdd.parent = dev;
0213     watchdog_set_nowayout(&pnx4008_wdd, nowayout);
0214     watchdog_set_restart_priority(&pnx4008_wdd, 128);
0215
0216     if (readl(WDTIM_CTRL(wdt_base)) & COUNT_ENAB)
0217         set_bit(WDOG_HW_RUNNING, &pnx4008_wdd.status);
0218
0219     ret = devm_watchdog_register_device(dev, &pnx4008_wdd);
0220     if (ret < 0)
0221         return ret;
0222
0223     dev_info(dev, "heartbeat %d sec\n", pnx4008_wdd.timeout);
0224
0225     return 0;
0226 }
0227
0228 #ifdef CONFIG_OF
0229 static const struct of_device_id pnx4008_wdt_match[] = {
0230     { .compatible = "nxp,pnx4008-wdt" },
0231     { }
0232 };
0233 MODULE_DEVICE_TABLE(of, pnx4008_wdt_match);
0234 #endif
0235
0236 static struct platform_driver platform_wdt_driver = {
0237     .driver = {
0238         .name = "pnx4008-watchdog",
0239         .of_match_table = of_match_ptr(pnx4008_wdt_match),
0240     },
0241     .probe = pnx4008_wdt_probe,
0242 };
0243
0244 module_platform_driver(platform_wdt_driver);
0245
0246 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
0247 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
0248 MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
0249
0250 module_param(heartbeat, uint, 0);
0251 MODULE_PARM_DESC(heartbeat,
0252          "Watchdog heartbeat period in seconds from 1 to "
0253          __MODULE_STRING(MAX_HEARTBEAT) ", default "
0254          __MODULE_STRING(DEFAULT_HEARTBEAT));
0255
0256 module_param(nowayout, bool, 0);
0257 MODULE_PARM_DESC(nowayout,
0258          "Set to 1 to keep watchdog running after device release");
0259
0260 MODULE_LICENSE("GPL");
0261 MODULE_ALIAS("platform:pnx4008-watchdog");