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0001 /*
0002  * drivers/watchdog/orion_wdt.c
0003  *
0004  * Watchdog driver for Orion/Kirkwood processors
0005  *
0006  * Author: Sylver Bruneau <sylver.bruneau@googlemail.com>
0007  *
0008  * This file is licensed under  the terms of the GNU General Public
0009  * License version 2. This program is licensed "as is" without any
0010  * warranty of any kind, whether express or implied.
0011  */
0012 
0013 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0014 
0015 #include <linux/module.h>
0016 #include <linux/moduleparam.h>
0017 #include <linux/types.h>
0018 #include <linux/kernel.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/watchdog.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/io.h>
0023 #include <linux/clk.h>
0024 #include <linux/err.h>
0025 #include <linux/of.h>
0026 #include <linux/of_device.h>
0027 
0028 /* RSTOUT mask register physical address for Orion5x, Kirkwood and Dove */
0029 #define ORION_RSTOUT_MASK_OFFSET    0x20108
0030 
0031 /* Internal registers can be configured at any 1 MiB aligned address */
0032 #define INTERNAL_REGS_MASK      ~(SZ_1M - 1)
0033 
0034 /*
0035  * Watchdog timer block registers.
0036  */
0037 #define TIMER_CTRL      0x0000
0038 #define TIMER1_FIXED_ENABLE_BIT BIT(12)
0039 #define WDT_AXP_FIXED_ENABLE_BIT BIT(10)
0040 #define TIMER1_ENABLE_BIT   BIT(2)
0041 
0042 #define TIMER_A370_STATUS   0x0004
0043 #define WDT_A370_EXPIRED    BIT(31)
0044 #define TIMER1_STATUS_BIT   BIT(8)
0045 
0046 #define TIMER1_VAL_OFF      0x001c
0047 
0048 #define WDT_MAX_CYCLE_COUNT 0xffffffff
0049 
0050 #define WDT_A370_RATIO_MASK(v)  ((v) << 16)
0051 #define WDT_A370_RATIO_SHIFT    5
0052 #define WDT_A370_RATIO      (1 << WDT_A370_RATIO_SHIFT)
0053 
0054 static bool nowayout = WATCHDOG_NOWAYOUT;
0055 static int heartbeat;       /* module parameter (seconds) */
0056 
0057 struct orion_watchdog;
0058 
0059 struct orion_watchdog_data {
0060     int wdt_counter_offset;
0061     int wdt_enable_bit;
0062     int rstout_enable_bit;
0063     int rstout_mask_bit;
0064     int (*clock_init)(struct platform_device *,
0065               struct orion_watchdog *);
0066     int (*enabled)(struct orion_watchdog *);
0067     int (*start)(struct watchdog_device *);
0068     int (*stop)(struct watchdog_device *);
0069 };
0070 
0071 struct orion_watchdog {
0072     struct watchdog_device wdt;
0073     void __iomem *reg;
0074     void __iomem *rstout;
0075     void __iomem *rstout_mask;
0076     unsigned long clk_rate;
0077     struct clk *clk;
0078     const struct orion_watchdog_data *data;
0079 };
0080 
0081 static int orion_wdt_clock_init(struct platform_device *pdev,
0082                 struct orion_watchdog *dev)
0083 {
0084     int ret;
0085 
0086     dev->clk = clk_get(&pdev->dev, NULL);
0087     if (IS_ERR(dev->clk))
0088         return PTR_ERR(dev->clk);
0089     ret = clk_prepare_enable(dev->clk);
0090     if (ret) {
0091         clk_put(dev->clk);
0092         return ret;
0093     }
0094 
0095     dev->clk_rate = clk_get_rate(dev->clk);
0096     return 0;
0097 }
0098 
0099 static int armada370_wdt_clock_init(struct platform_device *pdev,
0100                     struct orion_watchdog *dev)
0101 {
0102     int ret;
0103 
0104     dev->clk = clk_get(&pdev->dev, NULL);
0105     if (IS_ERR(dev->clk))
0106         return PTR_ERR(dev->clk);
0107     ret = clk_prepare_enable(dev->clk);
0108     if (ret) {
0109         clk_put(dev->clk);
0110         return ret;
0111     }
0112 
0113     /* Setup watchdog input clock */
0114     atomic_io_modify(dev->reg + TIMER_CTRL,
0115             WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT),
0116             WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT));
0117 
0118     dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO;
0119     return 0;
0120 }
0121 
0122 static int armada375_wdt_clock_init(struct platform_device *pdev,
0123                     struct orion_watchdog *dev)
0124 {
0125     int ret;
0126 
0127     dev->clk = of_clk_get_by_name(pdev->dev.of_node, "fixed");
0128     if (!IS_ERR(dev->clk)) {
0129         ret = clk_prepare_enable(dev->clk);
0130         if (ret) {
0131             clk_put(dev->clk);
0132             return ret;
0133         }
0134 
0135         atomic_io_modify(dev->reg + TIMER_CTRL,
0136                 WDT_AXP_FIXED_ENABLE_BIT,
0137                 WDT_AXP_FIXED_ENABLE_BIT);
0138         dev->clk_rate = clk_get_rate(dev->clk);
0139 
0140         return 0;
0141     }
0142 
0143     /* Mandatory fallback for proper devicetree backward compatibility */
0144     dev->clk = clk_get(&pdev->dev, NULL);
0145     if (IS_ERR(dev->clk))
0146         return PTR_ERR(dev->clk);
0147 
0148     ret = clk_prepare_enable(dev->clk);
0149     if (ret) {
0150         clk_put(dev->clk);
0151         return ret;
0152     }
0153 
0154     atomic_io_modify(dev->reg + TIMER_CTRL,
0155             WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT),
0156             WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT));
0157     dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO;
0158 
0159     return 0;
0160 }
0161 
0162 static int armadaxp_wdt_clock_init(struct platform_device *pdev,
0163                    struct orion_watchdog *dev)
0164 {
0165     int ret;
0166     u32 val;
0167 
0168     dev->clk = of_clk_get_by_name(pdev->dev.of_node, "fixed");
0169     if (IS_ERR(dev->clk))
0170         return PTR_ERR(dev->clk);
0171     ret = clk_prepare_enable(dev->clk);
0172     if (ret) {
0173         clk_put(dev->clk);
0174         return ret;
0175     }
0176 
0177     /* Fix the wdt and timer1 clock frequency to 25MHz */
0178     val = WDT_AXP_FIXED_ENABLE_BIT | TIMER1_FIXED_ENABLE_BIT;
0179     atomic_io_modify(dev->reg + TIMER_CTRL, val, val);
0180 
0181     dev->clk_rate = clk_get_rate(dev->clk);
0182     return 0;
0183 }
0184 
0185 static int orion_wdt_ping(struct watchdog_device *wdt_dev)
0186 {
0187     struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
0188     /* Reload watchdog duration */
0189     writel(dev->clk_rate * wdt_dev->timeout,
0190            dev->reg + dev->data->wdt_counter_offset);
0191     if (dev->wdt.info->options & WDIOF_PRETIMEOUT)
0192         writel(dev->clk_rate * (wdt_dev->timeout - wdt_dev->pretimeout),
0193                dev->reg + TIMER1_VAL_OFF);
0194 
0195     return 0;
0196 }
0197 
0198 static int armada375_start(struct watchdog_device *wdt_dev)
0199 {
0200     struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
0201     u32 reg;
0202 
0203     /* Set watchdog duration */
0204     writel(dev->clk_rate * wdt_dev->timeout,
0205            dev->reg + dev->data->wdt_counter_offset);
0206     if (dev->wdt.info->options & WDIOF_PRETIMEOUT)
0207         writel(dev->clk_rate * (wdt_dev->timeout - wdt_dev->pretimeout),
0208                dev->reg + TIMER1_VAL_OFF);
0209 
0210     /* Clear the watchdog expiration bit */
0211     atomic_io_modify(dev->reg + TIMER_A370_STATUS, WDT_A370_EXPIRED, 0);
0212 
0213     /* Enable watchdog timer */
0214     reg = dev->data->wdt_enable_bit;
0215     if (dev->wdt.info->options & WDIOF_PRETIMEOUT)
0216         reg |= TIMER1_ENABLE_BIT;
0217     atomic_io_modify(dev->reg + TIMER_CTRL, reg, reg);
0218 
0219     /* Enable reset on watchdog */
0220     reg = readl(dev->rstout);
0221     reg |= dev->data->rstout_enable_bit;
0222     writel(reg, dev->rstout);
0223 
0224     atomic_io_modify(dev->rstout_mask, dev->data->rstout_mask_bit, 0);
0225     return 0;
0226 }
0227 
0228 static int armada370_start(struct watchdog_device *wdt_dev)
0229 {
0230     struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
0231     u32 reg;
0232 
0233     /* Set watchdog duration */
0234     writel(dev->clk_rate * wdt_dev->timeout,
0235            dev->reg + dev->data->wdt_counter_offset);
0236 
0237     /* Clear the watchdog expiration bit */
0238     atomic_io_modify(dev->reg + TIMER_A370_STATUS, WDT_A370_EXPIRED, 0);
0239 
0240     /* Enable watchdog timer */
0241     reg = dev->data->wdt_enable_bit;
0242     if (dev->wdt.info->options & WDIOF_PRETIMEOUT)
0243         reg |= TIMER1_ENABLE_BIT;
0244     atomic_io_modify(dev->reg + TIMER_CTRL, reg, reg);
0245 
0246     /* Enable reset on watchdog */
0247     reg = readl(dev->rstout);
0248     reg |= dev->data->rstout_enable_bit;
0249     writel(reg, dev->rstout);
0250     return 0;
0251 }
0252 
0253 static int orion_start(struct watchdog_device *wdt_dev)
0254 {
0255     struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
0256 
0257     /* Set watchdog duration */
0258     writel(dev->clk_rate * wdt_dev->timeout,
0259            dev->reg + dev->data->wdt_counter_offset);
0260 
0261     /* Enable watchdog timer */
0262     atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit,
0263                         dev->data->wdt_enable_bit);
0264 
0265     /* Enable reset on watchdog */
0266     atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit,
0267                       dev->data->rstout_enable_bit);
0268 
0269     return 0;
0270 }
0271 
0272 static int orion_wdt_start(struct watchdog_device *wdt_dev)
0273 {
0274     struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
0275 
0276     /* There are some per-SoC quirks to handle */
0277     return dev->data->start(wdt_dev);
0278 }
0279 
0280 static int orion_stop(struct watchdog_device *wdt_dev)
0281 {
0282     struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
0283 
0284     /* Disable reset on watchdog */
0285     atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit, 0);
0286 
0287     /* Disable watchdog timer */
0288     atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0);
0289 
0290     return 0;
0291 }
0292 
0293 static int armada375_stop(struct watchdog_device *wdt_dev)
0294 {
0295     struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
0296     u32 reg, mask;
0297 
0298     /* Disable reset on watchdog */
0299     atomic_io_modify(dev->rstout_mask, dev->data->rstout_mask_bit,
0300                        dev->data->rstout_mask_bit);
0301     reg = readl(dev->rstout);
0302     reg &= ~dev->data->rstout_enable_bit;
0303     writel(reg, dev->rstout);
0304 
0305     /* Disable watchdog timer */
0306     mask = dev->data->wdt_enable_bit;
0307     if (wdt_dev->info->options & WDIOF_PRETIMEOUT)
0308         mask |= TIMER1_ENABLE_BIT;
0309     atomic_io_modify(dev->reg + TIMER_CTRL, mask, 0);
0310 
0311     return 0;
0312 }
0313 
0314 static int armada370_stop(struct watchdog_device *wdt_dev)
0315 {
0316     struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
0317     u32 reg, mask;
0318 
0319     /* Disable reset on watchdog */
0320     reg = readl(dev->rstout);
0321     reg &= ~dev->data->rstout_enable_bit;
0322     writel(reg, dev->rstout);
0323 
0324     /* Disable watchdog timer */
0325     mask = dev->data->wdt_enable_bit;
0326     if (wdt_dev->info->options & WDIOF_PRETIMEOUT)
0327         mask |= TIMER1_ENABLE_BIT;
0328     atomic_io_modify(dev->reg + TIMER_CTRL, mask, 0);
0329 
0330     return 0;
0331 }
0332 
0333 static int orion_wdt_stop(struct watchdog_device *wdt_dev)
0334 {
0335     struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
0336 
0337     return dev->data->stop(wdt_dev);
0338 }
0339 
0340 static int orion_enabled(struct orion_watchdog *dev)
0341 {
0342     bool enabled, running;
0343 
0344     enabled = readl(dev->rstout) & dev->data->rstout_enable_bit;
0345     running = readl(dev->reg + TIMER_CTRL) & dev->data->wdt_enable_bit;
0346 
0347     return enabled && running;
0348 }
0349 
0350 static int armada375_enabled(struct orion_watchdog *dev)
0351 {
0352     bool masked, enabled, running;
0353 
0354     masked = readl(dev->rstout_mask) & dev->data->rstout_mask_bit;
0355     enabled = readl(dev->rstout) & dev->data->rstout_enable_bit;
0356     running = readl(dev->reg + TIMER_CTRL) & dev->data->wdt_enable_bit;
0357 
0358     return !masked && enabled && running;
0359 }
0360 
0361 static int orion_wdt_enabled(struct watchdog_device *wdt_dev)
0362 {
0363     struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
0364 
0365     return dev->data->enabled(dev);
0366 }
0367 
0368 static unsigned int orion_wdt_get_timeleft(struct watchdog_device *wdt_dev)
0369 {
0370     struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
0371     return readl(dev->reg + dev->data->wdt_counter_offset) / dev->clk_rate;
0372 }
0373 
0374 static struct watchdog_info orion_wdt_info = {
0375     .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
0376     .identity = "Orion Watchdog",
0377 };
0378 
0379 static const struct watchdog_ops orion_wdt_ops = {
0380     .owner = THIS_MODULE,
0381     .start = orion_wdt_start,
0382     .stop = orion_wdt_stop,
0383     .ping = orion_wdt_ping,
0384     .get_timeleft = orion_wdt_get_timeleft,
0385 };
0386 
0387 static irqreturn_t orion_wdt_irq(int irq, void *devid)
0388 {
0389     panic("Watchdog Timeout");
0390     return IRQ_HANDLED;
0391 }
0392 
0393 static irqreturn_t orion_wdt_pre_irq(int irq, void *devid)
0394 {
0395     struct orion_watchdog *dev = devid;
0396 
0397     atomic_io_modify(dev->reg + TIMER_A370_STATUS,
0398              TIMER1_STATUS_BIT, 0);
0399     watchdog_notify_pretimeout(&dev->wdt);
0400     return IRQ_HANDLED;
0401 }
0402 
0403 /*
0404  * The original devicetree binding for this driver specified only
0405  * one memory resource, so in order to keep DT backwards compatibility
0406  * we try to fallback to a hardcoded register address, if the resource
0407  * is missing from the devicetree.
0408  */
0409 static void __iomem *orion_wdt_ioremap_rstout(struct platform_device *pdev,
0410                           phys_addr_t internal_regs)
0411 {
0412     struct resource *res;
0413     phys_addr_t rstout;
0414 
0415     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0416     if (res)
0417         return devm_ioremap(&pdev->dev, res->start,
0418                     resource_size(res));
0419 
0420     rstout = internal_regs + ORION_RSTOUT_MASK_OFFSET;
0421 
0422     WARN(1, FW_BUG "falling back to hardcoded RSTOUT reg %pa\n", &rstout);
0423     return devm_ioremap(&pdev->dev, rstout, 0x4);
0424 }
0425 
0426 static const struct orion_watchdog_data orion_data = {
0427     .rstout_enable_bit = BIT(1),
0428     .wdt_enable_bit = BIT(4),
0429     .wdt_counter_offset = 0x24,
0430     .clock_init = orion_wdt_clock_init,
0431     .enabled = orion_enabled,
0432     .start = orion_start,
0433     .stop = orion_stop,
0434 };
0435 
0436 static const struct orion_watchdog_data armada370_data = {
0437     .rstout_enable_bit = BIT(8),
0438     .wdt_enable_bit = BIT(8),
0439     .wdt_counter_offset = 0x34,
0440     .clock_init = armada370_wdt_clock_init,
0441     .enabled = orion_enabled,
0442     .start = armada370_start,
0443     .stop = armada370_stop,
0444 };
0445 
0446 static const struct orion_watchdog_data armadaxp_data = {
0447     .rstout_enable_bit = BIT(8),
0448     .wdt_enable_bit = BIT(8),
0449     .wdt_counter_offset = 0x34,
0450     .clock_init = armadaxp_wdt_clock_init,
0451     .enabled = orion_enabled,
0452     .start = armada370_start,
0453     .stop = armada370_stop,
0454 };
0455 
0456 static const struct orion_watchdog_data armada375_data = {
0457     .rstout_enable_bit = BIT(8),
0458     .rstout_mask_bit = BIT(10),
0459     .wdt_enable_bit = BIT(8),
0460     .wdt_counter_offset = 0x34,
0461     .clock_init = armada375_wdt_clock_init,
0462     .enabled = armada375_enabled,
0463     .start = armada375_start,
0464     .stop = armada375_stop,
0465 };
0466 
0467 static const struct orion_watchdog_data armada380_data = {
0468     .rstout_enable_bit = BIT(8),
0469     .rstout_mask_bit = BIT(10),
0470     .wdt_enable_bit = BIT(8),
0471     .wdt_counter_offset = 0x34,
0472     .clock_init = armadaxp_wdt_clock_init,
0473     .enabled = armada375_enabled,
0474     .start = armada375_start,
0475     .stop = armada375_stop,
0476 };
0477 
0478 static const struct of_device_id orion_wdt_of_match_table[] = {
0479     {
0480         .compatible = "marvell,orion-wdt",
0481         .data = &orion_data,
0482     },
0483     {
0484         .compatible = "marvell,armada-370-wdt",
0485         .data = &armada370_data,
0486     },
0487     {
0488         .compatible = "marvell,armada-xp-wdt",
0489         .data = &armadaxp_data,
0490     },
0491     {
0492         .compatible = "marvell,armada-375-wdt",
0493         .data = &armada375_data,
0494     },
0495     {
0496         .compatible = "marvell,armada-380-wdt",
0497         .data = &armada380_data,
0498     },
0499     {},
0500 };
0501 MODULE_DEVICE_TABLE(of, orion_wdt_of_match_table);
0502 
0503 static int orion_wdt_get_regs(struct platform_device *pdev,
0504                   struct orion_watchdog *dev)
0505 {
0506     struct device_node *node = pdev->dev.of_node;
0507     struct resource *res;
0508 
0509     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0510     if (!res)
0511         return -ENODEV;
0512     dev->reg = devm_ioremap(&pdev->dev, res->start,
0513                 resource_size(res));
0514     if (!dev->reg)
0515         return -ENOMEM;
0516 
0517     /* Each supported compatible has some RSTOUT register quirk */
0518     if (of_device_is_compatible(node, "marvell,orion-wdt")) {
0519 
0520         dev->rstout = orion_wdt_ioremap_rstout(pdev, res->start &
0521                                INTERNAL_REGS_MASK);
0522         if (!dev->rstout)
0523             return -ENODEV;
0524 
0525     } else if (of_device_is_compatible(node, "marvell,armada-370-wdt") ||
0526            of_device_is_compatible(node, "marvell,armada-xp-wdt")) {
0527 
0528         /* Dedicated RSTOUT register, can be requested. */
0529         dev->rstout = devm_platform_ioremap_resource(pdev, 1);
0530         if (IS_ERR(dev->rstout))
0531             return PTR_ERR(dev->rstout);
0532 
0533     } else if (of_device_is_compatible(node, "marvell,armada-375-wdt") ||
0534            of_device_is_compatible(node, "marvell,armada-380-wdt")) {
0535 
0536         /* Dedicated RSTOUT register, can be requested. */
0537         dev->rstout = devm_platform_ioremap_resource(pdev, 1);
0538         if (IS_ERR(dev->rstout))
0539             return PTR_ERR(dev->rstout);
0540 
0541         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
0542         if (!res)
0543             return -ENODEV;
0544         dev->rstout_mask = devm_ioremap(&pdev->dev, res->start,
0545                         resource_size(res));
0546         if (!dev->rstout_mask)
0547             return -ENOMEM;
0548 
0549     } else {
0550         return -ENODEV;
0551     }
0552 
0553     return 0;
0554 }
0555 
0556 static int orion_wdt_probe(struct platform_device *pdev)
0557 {
0558     struct orion_watchdog *dev;
0559     const struct of_device_id *match;
0560     unsigned int wdt_max_duration;  /* (seconds) */
0561     int ret, irq;
0562 
0563     dev = devm_kzalloc(&pdev->dev, sizeof(struct orion_watchdog),
0564                GFP_KERNEL);
0565     if (!dev)
0566         return -ENOMEM;
0567 
0568     match = of_match_device(orion_wdt_of_match_table, &pdev->dev);
0569     if (!match)
0570         /* Default legacy match */
0571         match = &orion_wdt_of_match_table[0];
0572 
0573     dev->wdt.info = &orion_wdt_info;
0574     dev->wdt.ops = &orion_wdt_ops;
0575     dev->wdt.min_timeout = 1;
0576     dev->data = match->data;
0577 
0578     ret = orion_wdt_get_regs(pdev, dev);
0579     if (ret)
0580         return ret;
0581 
0582     ret = dev->data->clock_init(pdev, dev);
0583     if (ret) {
0584         dev_err(&pdev->dev, "cannot initialize clock\n");
0585         return ret;
0586     }
0587 
0588     wdt_max_duration = WDT_MAX_CYCLE_COUNT / dev->clk_rate;
0589 
0590     dev->wdt.timeout = wdt_max_duration;
0591     dev->wdt.max_timeout = wdt_max_duration;
0592     dev->wdt.parent = &pdev->dev;
0593     watchdog_init_timeout(&dev->wdt, heartbeat, &pdev->dev);
0594 
0595     platform_set_drvdata(pdev, &dev->wdt);
0596     watchdog_set_drvdata(&dev->wdt, dev);
0597 
0598     /*
0599      * Let's make sure the watchdog is fully stopped, unless it's
0600      * explicitly enabled. This may be the case if the module was
0601      * removed and re-inserted, or if the bootloader explicitly
0602      * set a running watchdog before booting the kernel.
0603      */
0604     if (!orion_wdt_enabled(&dev->wdt))
0605         orion_wdt_stop(&dev->wdt);
0606     else
0607         set_bit(WDOG_HW_RUNNING, &dev->wdt.status);
0608 
0609     /* Request the IRQ only after the watchdog is disabled */
0610     irq = platform_get_irq_optional(pdev, 0);
0611     if (irq > 0) {
0612         /*
0613          * Not all supported platforms specify an interrupt for the
0614          * watchdog, so let's make it optional.
0615          */
0616         ret = devm_request_irq(&pdev->dev, irq, orion_wdt_irq, 0,
0617                        pdev->name, dev);
0618         if (ret < 0) {
0619             dev_err(&pdev->dev, "failed to request IRQ\n");
0620             goto disable_clk;
0621         }
0622     }
0623 
0624     /* Optional 2nd interrupt for pretimeout */
0625     irq = platform_get_irq_optional(pdev, 1);
0626     if (irq > 0) {
0627         orion_wdt_info.options |= WDIOF_PRETIMEOUT;
0628         ret = devm_request_irq(&pdev->dev, irq, orion_wdt_pre_irq,
0629                        0, pdev->name, dev);
0630         if (ret < 0) {
0631             dev_err(&pdev->dev, "failed to request IRQ\n");
0632             goto disable_clk;
0633         }
0634     }
0635 
0636 
0637     watchdog_set_nowayout(&dev->wdt, nowayout);
0638     ret = watchdog_register_device(&dev->wdt);
0639     if (ret)
0640         goto disable_clk;
0641 
0642     pr_info("Initial timeout %d sec%s\n",
0643         dev->wdt.timeout, nowayout ? ", nowayout" : "");
0644     return 0;
0645 
0646 disable_clk:
0647     clk_disable_unprepare(dev->clk);
0648     clk_put(dev->clk);
0649     return ret;
0650 }
0651 
0652 static int orion_wdt_remove(struct platform_device *pdev)
0653 {
0654     struct watchdog_device *wdt_dev = platform_get_drvdata(pdev);
0655     struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
0656 
0657     watchdog_unregister_device(wdt_dev);
0658     clk_disable_unprepare(dev->clk);
0659     clk_put(dev->clk);
0660     return 0;
0661 }
0662 
0663 static void orion_wdt_shutdown(struct platform_device *pdev)
0664 {
0665     struct watchdog_device *wdt_dev = platform_get_drvdata(pdev);
0666     orion_wdt_stop(wdt_dev);
0667 }
0668 
0669 static struct platform_driver orion_wdt_driver = {
0670     .probe      = orion_wdt_probe,
0671     .remove     = orion_wdt_remove,
0672     .shutdown   = orion_wdt_shutdown,
0673     .driver     = {
0674         .name   = "orion_wdt",
0675         .of_match_table = orion_wdt_of_match_table,
0676     },
0677 };
0678 
0679 module_platform_driver(orion_wdt_driver);
0680 
0681 MODULE_AUTHOR("Sylver Bruneau <sylver.bruneau@googlemail.com>");
0682 MODULE_DESCRIPTION("Orion Processor Watchdog");
0683 
0684 module_param(heartbeat, int, 0);
0685 MODULE_PARM_DESC(heartbeat, "Initial watchdog heartbeat in seconds");
0686 
0687 module_param(nowayout, bool, 0);
0688 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
0689                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
0690 
0691 MODULE_LICENSE("GPL v2");
0692 MODULE_ALIAS("platform:orion_wdt");
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