drivers/watchdog/of_xilinx_wdt.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
0004  *
0005  * (C) Copyright 2013 - 2014 Xilinx, Inc.
0006  * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>)
0007  */
0008
0009 #include <linux/bits.h>
0010 #include <linux/clk.h>
0011 #include <linux/err.h>
0012 #include <linux/module.h>
0013 #include <linux/types.h>
0014 #include <linux/kernel.h>
0015 #include <linux/ioport.h>
0016 #include <linux/watchdog.h>
0017 #include <linux/io.h>
0018 #include <linux/of.h>
0019 #include <linux/of_device.h>
0020 #include <linux/of_address.h>
0021
0022 /* Register offsets for the Wdt device */
0023 #define XWT_TWCSR0_OFFSET   0x0 /* Control/Status Register0 */
0024 #define XWT_TWCSR1_OFFSET   0x4 /* Control/Status Register1 */
0025 #define XWT_TBR_OFFSET      0x8 /* Timebase Register Offset */
0026
0027 /* Control/Status Register Masks  */
0028 #define XWT_CSR0_WRS_MASK   BIT(3) /* Reset status */
0029 #define XWT_CSR0_WDS_MASK   BIT(2) /* Timer state  */
0030 #define XWT_CSR0_EWDT1_MASK BIT(1) /* Enable bit 1 */
0031
0032 /* Control/Status Register 0/1 bits  */
0033 #define XWT_CSRX_EWDT2_MASK BIT(0) /* Enable bit 2 */
0034
0035 /* SelfTest constants */
0036 #define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000
0037 #define XWT_TIMER_FAILED            0xFFFFFFFF
0038
0039 #define WATCHDOG_NAME     "Xilinx Watchdog"
0040
0041 struct xwdt_device {
0042     void __iomem *base;
0043     u32 wdt_interval;
0044     spinlock_t spinlock; /* spinlock for register handling */
0045     struct watchdog_device xilinx_wdt_wdd;
0046     struct clk      *clk;
0047 };
0048
0049 static int xilinx_wdt_start(struct watchdog_device *wdd)
0050 {
0051     int ret;
0052     u32 control_status_reg;
0053     struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
0054
0055     ret = clk_enable(xdev->clk);
0056     if (ret) {
0057         dev_err(wdd->parent, "Failed to enable clock\n");
0058         return ret;
0059     }
0060
0061     spin_lock(&xdev->spinlock);
0062
0063     /* Clean previous status and enable the watchdog timer */
0064     control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
0065     control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
0066
0067     iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK),
0068           xdev->base + XWT_TWCSR0_OFFSET);
0069
0070     iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET);
0071
0072     spin_unlock(&xdev->spinlock);
0073
0074     dev_dbg(wdd->parent, "Watchdog Started!\n");
0075
0076     return 0;
0077 }
0078
0079 static int xilinx_wdt_stop(struct watchdog_device *wdd)
0080 {
0081     u32 control_status_reg;
0082     struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
0083
0084     spin_lock(&xdev->spinlock);
0085
0086     control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
0087
0088     iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK),
0089           xdev->base + XWT_TWCSR0_OFFSET);
0090
0091     iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET);
0092
0093     spin_unlock(&xdev->spinlock);
0094
0095     clk_disable(xdev->clk);
0096
0097     dev_dbg(wdd->parent, "Watchdog Stopped!\n");
0098
0099     return 0;
0100 }
0101
0102 static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
0103 {
0104     u32 control_status_reg;
0105     struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
0106
0107     spin_lock(&xdev->spinlock);
0108
0109     control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
0110     control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
0111     iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET);
0112
0113     spin_unlock(&xdev->spinlock);
0114
0115     return 0;
0116 }
0117
0118 static const struct watchdog_info xilinx_wdt_ident = {
0119     .options =  WDIOF_MAGICCLOSE |
0120             WDIOF_KEEPALIVEPING,
0121     .firmware_version = 1,
0122     .identity = WATCHDOG_NAME,
0123 };
0124
0125 static const struct watchdog_ops xilinx_wdt_ops = {
0126     .owner = THIS_MODULE,
0127     .start = xilinx_wdt_start,
0128     .stop = xilinx_wdt_stop,
0129     .ping = xilinx_wdt_keepalive,
0130 };
0131
0132 static u32 xwdt_selftest(struct xwdt_device *xdev)
0133 {
0134     int i;
0135     u32 timer_value1;
0136     u32 timer_value2;
0137
0138     spin_lock(&xdev->spinlock);
0139
0140     timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET);
0141     timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
0142
0143     for (i = 0;
0144         ((i <= XWT_MAX_SELFTEST_LOOP_COUNT) &&
0145             (timer_value2 == timer_value1)); i++) {
0146         timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
0147     }
0148
0149     spin_unlock(&xdev->spinlock);
0150
0151     if (timer_value2 != timer_value1)
0152         return ~XWT_TIMER_FAILED;
0153     else
0154         return XWT_TIMER_FAILED;
0155 }
0156
0157 static void xwdt_clk_disable_unprepare(void *data)
0158 {
0159     clk_disable_unprepare(data);
0160 }
0161
0162 static int xwdt_probe(struct platform_device *pdev)
0163 {
0164     struct device *dev = &pdev->dev;
0165     int rc;
0166     u32 pfreq = 0, enable_once = 0;
0167     struct xwdt_device *xdev;
0168     struct watchdog_device *xilinx_wdt_wdd;
0169
0170     xdev = devm_kzalloc(dev, sizeof(*xdev), GFP_KERNEL);
0171     if (!xdev)
0172         return -ENOMEM;
0173
0174     xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd;
0175     xilinx_wdt_wdd->info = &xilinx_wdt_ident;
0176     xilinx_wdt_wdd->ops = &xilinx_wdt_ops;
0177     xilinx_wdt_wdd->parent = dev;
0178
0179     xdev->base = devm_platform_ioremap_resource(pdev, 0);
0180     if (IS_ERR(xdev->base))
0181         return PTR_ERR(xdev->base);
0182
0183     rc = of_property_read_u32(dev->of_node, "xlnx,wdt-interval",
0184                   &xdev->wdt_interval);
0185     if (rc)
0186         dev_warn(dev, "Parameter \"xlnx,wdt-interval\" not found\n");
0187
0188     rc = of_property_read_u32(dev->of_node, "xlnx,wdt-enable-once",
0189                   &enable_once);
0190     if (rc)
0191         dev_warn(dev,
0192              "Parameter \"xlnx,wdt-enable-once\" not found\n");
0193
0194     watchdog_set_nowayout(xilinx_wdt_wdd, enable_once);
0195
0196     xdev->clk = devm_clk_get(dev, NULL);
0197     if (IS_ERR(xdev->clk)) {
0198         if (PTR_ERR(xdev->clk) != -ENOENT)
0199             return PTR_ERR(xdev->clk);
0200
0201         /*
0202          * Clock framework support is optional, continue on
0203          * anyways if we don't find a matching clock.
0204          */
0205         xdev->clk = NULL;
0206
0207         rc = of_property_read_u32(dev->of_node, "clock-frequency",
0208                       &pfreq);
0209         if (rc)
0210             dev_warn(dev,
0211                  "The watchdog clock freq cannot be obtained\n");
0212     } else {
0213         pfreq = clk_get_rate(xdev->clk);
0214         rc = clk_prepare_enable(xdev->clk);
0215         if (rc) {
0216             dev_err(dev, "unable to enable clock\n");
0217             return rc;
0218         }
0219         rc = devm_add_action_or_reset(dev, xwdt_clk_disable_unprepare,
0220                           xdev->clk);
0221         if (rc)
0222             return rc;
0223     }
0224
0225     /*
0226      * Twice of the 2^wdt_interval / freq  because the first wdt overflow is
0227      * ignored (interrupt), reset is only generated at second wdt overflow
0228      */
0229     if (pfreq && xdev->wdt_interval)
0230         xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /
0231                       pfreq);
0232
0233     spin_lock_init(&xdev->spinlock);
0234     watchdog_set_drvdata(xilinx_wdt_wdd, xdev);
0235
0236     rc = xwdt_selftest(xdev);
0237     if (rc == XWT_TIMER_FAILED) {
0238         dev_err(dev, "SelfTest routine error\n");
0239         return rc;
0240     }
0241
0242     rc = devm_watchdog_register_device(dev, xilinx_wdt_wdd);
0243     if (rc)
0244         return rc;
0245
0246     clk_disable(xdev->clk);
0247
0248     dev_info(dev, "Xilinx Watchdog Timer with timeout %ds\n",
0249          xilinx_wdt_wdd->timeout);
0250
0251     platform_set_drvdata(pdev, xdev);
0252
0253     return 0;
0254 }
0255
0256 /**
0257  * xwdt_suspend - Suspend the device.
0258  *
0259  * @dev: handle to the device structure.
0260  * Return: 0 always.
0261  */
0262 static int __maybe_unused xwdt_suspend(struct device *dev)
0263 {
0264     struct xwdt_device *xdev = dev_get_drvdata(dev);
0265
0266     if (watchdog_active(&xdev->xilinx_wdt_wdd))
0267         xilinx_wdt_stop(&xdev->xilinx_wdt_wdd);
0268
0269     return 0;
0270 }
0271
0272 /**
0273  * xwdt_resume - Resume the device.
0274  *
0275  * @dev: handle to the device structure.
0276  * Return: 0 on success, errno otherwise.
0277  */
0278 static int __maybe_unused xwdt_resume(struct device *dev)
0279 {
0280     struct xwdt_device *xdev = dev_get_drvdata(dev);
0281     int ret = 0;
0282
0283     if (watchdog_active(&xdev->xilinx_wdt_wdd))
0284         ret = xilinx_wdt_start(&xdev->xilinx_wdt_wdd);
0285
0286     return ret;
0287 }
0288
0289 static SIMPLE_DEV_PM_OPS(xwdt_pm_ops, xwdt_suspend, xwdt_resume);
0290
0291 /* Match table for of_platform binding */
0292 static const struct of_device_id xwdt_of_match[] = {
0293     { .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
0294     { .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
0295     {},
0296 };
0297 MODULE_DEVICE_TABLE(of, xwdt_of_match);
0298
0299 static struct platform_driver xwdt_driver = {
0300     .probe       = xwdt_probe,
0301     .driver = {
0302         .name  = WATCHDOG_NAME,
0303         .of_match_table = xwdt_of_match,
0304         .pm = &xwdt_pm_ops,
0305     },
0306 };
0307
0308 module_platform_driver(xwdt_driver);
0309
0310 MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>");
0311 MODULE_DESCRIPTION("Xilinx Watchdog driver");
0312 MODULE_LICENSE("GPL");