drivers/watchdog/nv_tco.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  *  nv_tco: TCO timer driver for nVidia chipsets.
0004  *
0005  *  (c) Copyright 2005 Google Inc., All Rights Reserved.
0006  *
0007  *  Supported Chipsets:
0008  *      - MCP51/MCP55
0009  *
0010  *  (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
0011  *  Reserved.
0012  *              https://www.kernelconcepts.de
0013  *
0014  *  Neither kernel concepts nor Nils Faerber admit liability nor provide
0015  *  warranty for any of this software. This material is provided
0016  *  "AS-IS" and at no charge.
0017  *
0018  *  (c) Copyright 2000  kernel concepts <nils@kernelconcepts.de>
0019  *              developed for
0020  *                              Jentro AG, Haar/Munich (Germany)
0021  *
0022  *  TCO timer driver for NV chipsets
0023  *  based on softdog.c by Alan Cox <alan@redhat.com>
0024  */
0025
0026 /*
0027  * Some address definitions for the TCO
0028  */
0029
0030 #define TCO_RLD(base)   ((base) + 0x00) /* TCO Timer Reload and Current Value */
0031 #define TCO_TMR(base)   ((base) + 0x01) /* TCO Timer Initial Value  */
0032
0033 #define TCO_STS(base)   ((base) + 0x04) /* TCO Status Register      */
0034 /*
0035  * TCO Boot Status bit: set on TCO reset, reset by software or standby
0036  * power-good (survives reboots), unfortunately this bit is never
0037  * set.
0038  */
0039 #  define TCO_STS_BOOT_STS  (1 << 9)
0040 /*
0041  * first and 2nd timeout status bits, these also survive a warm boot,
0042  * and they work, so we use them.
0043  */
0044 #  define TCO_STS_TCO_INT_STS   (1 << 1)
0045 #  define TCO_STS_TCO2TO_STS    (1 << 10)
0046 #  define TCO_STS_RESET     (TCO_STS_BOOT_STS | TCO_STS_TCO2TO_STS | \
0047                  TCO_STS_TCO_INT_STS)
0048
0049 #define TCO_CNT(base)   ((base) + 0x08) /* TCO Control Register */
0050 #  define TCO_CNT_TCOHALT   (1 << 12)
0051
0052 #define MCP51_SMBUS_SETUP_B 0xe8
0053 #  define MCP51_SMBUS_SETUP_B_TCO_REBOOT (1 << 25)
0054
0055 /*
0056  * The SMI_EN register is at the base io address + 0x04,
0057  * while TCOBASE is + 0x40.
0058  */
0059 #define MCP51_SMI_EN(base)  ((base) - 0x40 + 0x04)
0060 #  define MCP51_SMI_EN_TCO  ((1 << 4) | (1 << 5))