drivers/watchdog/mtk_wdt.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Mediatek Watchdog Driver
0004  *
0005  * Copyright (C) 2014 Matthias Brugger
0006  *
0007  * Matthias Brugger <matthias.bgg@gmail.com>
0008  *
0009  * Based on sunxi_wdt.c
0010  */
0011
0012 #include <dt-bindings/reset/mt2712-resets.h>
0013 #include <dt-bindings/reset/mt7986-resets.h>
0014 #include <dt-bindings/reset/mt8183-resets.h>
0015 #include <dt-bindings/reset/mt8186-resets.h>
0016 #include <dt-bindings/reset/mt8192-resets.h>
0017 #include <dt-bindings/reset/mt8195-resets.h>
0018 #include <linux/delay.h>
0019 #include <linux/err.h>
0020 #include <linux/init.h>
0021 #include <linux/io.h>
0022 #include <linux/kernel.h>
0023 #include <linux/module.h>
0024 #include <linux/moduleparam.h>
0025 #include <linux/of.h>
0026 #include <linux/of_device.h>
0027 #include <linux/platform_device.h>
0028 #include <linux/reset-controller.h>
0029 #include <linux/types.h>
0030 #include <linux/watchdog.h>
0031 #include <linux/interrupt.h>
0032
0033 #define WDT_MAX_TIMEOUT     31
0034 #define WDT_MIN_TIMEOUT     2
0035 #define WDT_LENGTH_TIMEOUT(n)   ((n) << 5)
0036
0037 #define WDT_LENGTH      0x04
0038 #define WDT_LENGTH_KEY      0x8
0039
0040 #define WDT_RST         0x08
0041 #define WDT_RST_RELOAD      0x1971
0042
0043 #define WDT_MODE        0x00
0044 #define WDT_MODE_EN     (1 << 0)
0045 #define WDT_MODE_EXT_POL_LOW    (0 << 1)
0046 #define WDT_MODE_EXT_POL_HIGH   (1 << 1)
0047 #define WDT_MODE_EXRST_EN   (1 << 2)
0048 #define WDT_MODE_IRQ_EN     (1 << 3)
0049 #define WDT_MODE_AUTO_START (1 << 4)
0050 #define WDT_MODE_DUAL_EN    (1 << 6)
0051 #define WDT_MODE_KEY        0x22000000
0052
0053 #define WDT_SWRST       0x14
0054 #define WDT_SWRST_KEY       0x1209
0055
0056 #define WDT_SWSYSRST        0x18U
0057 #define WDT_SWSYS_RST_KEY   0x88000000
0058
0059 #define DRV_NAME        "mtk-wdt"
0060 #define DRV_VERSION     "1.0"
0061
0062 static bool nowayout = WATCHDOG_NOWAYOUT;
0063 static unsigned int timeout;
0064
0065 struct mtk_wdt_dev {
0066     struct watchdog_device wdt_dev;
0067     void __iomem *wdt_base;
0068     spinlock_t lock; /* protects WDT_SWSYSRST reg */
0069     struct reset_controller_dev rcdev;
0070     bool disable_wdt_extrst;
0071 };
0072
0073 struct mtk_wdt_data {
0074     int toprgu_sw_rst_num;
0075 };
0076
0077 static const struct mtk_wdt_data mt2712_data = {
0078     .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
0079 };
0080
0081 static const struct mtk_wdt_data mt7986_data = {
0082     .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
0083 };
0084
0085 static const struct mtk_wdt_data mt8183_data = {
0086     .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
0087 };
0088
0089 static const struct mtk_wdt_data mt8186_data = {
0090     .toprgu_sw_rst_num = MT8186_TOPRGU_SW_RST_NUM,
0091 };
0092
0093 static const struct mtk_wdt_data mt8192_data = {
0094     .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
0095 };
0096
0097 static const struct mtk_wdt_data mt8195_data = {
0098     .toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
0099 };
0100
0101 static int toprgu_reset_update(struct reset_controller_dev *rcdev,
0102                    unsigned long id, bool assert)
0103 {
0104     unsigned int tmp;
0105     unsigned long flags;
0106     struct mtk_wdt_dev *data =
0107          container_of(rcdev, struct mtk_wdt_dev, rcdev);
0108
0109     spin_lock_irqsave(&data->lock, flags);
0110
0111     tmp = readl(data->wdt_base + WDT_SWSYSRST);
0112     if (assert)
0113         tmp |= BIT(id);
0114     else
0115         tmp &= ~BIT(id);
0116     tmp |= WDT_SWSYS_RST_KEY;
0117     writel(tmp, data->wdt_base + WDT_SWSYSRST);
0118
0119     spin_unlock_irqrestore(&data->lock, flags);
0120
0121     return 0;
0122 }
0123
0124 static int toprgu_reset_assert(struct reset_controller_dev *rcdev,
0125                    unsigned long id)
0126 {
0127     return toprgu_reset_update(rcdev, id, true);
0128 }
0129
0130 static int toprgu_reset_deassert(struct reset_controller_dev *rcdev,
0131                  unsigned long id)
0132 {
0133     return toprgu_reset_update(rcdev, id, false);
0134 }
0135
0136 static int toprgu_reset(struct reset_controller_dev *rcdev,
0137             unsigned long id)
0138 {
0139     int ret;
0140
0141     ret = toprgu_reset_assert(rcdev, id);
0142     if (ret)
0143         return ret;
0144
0145     return toprgu_reset_deassert(rcdev, id);
0146 }
0147
0148 static const struct reset_control_ops toprgu_reset_ops = {
0149     .assert = toprgu_reset_assert,
0150     .deassert = toprgu_reset_deassert,
0151     .reset = toprgu_reset,
0152 };
0153
0154 static int toprgu_register_reset_controller(struct platform_device *pdev,
0155                         int rst_num)
0156 {
0157     int ret;
0158     struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
0159
0160     spin_lock_init(&mtk_wdt->lock);
0161
0162     mtk_wdt->rcdev.owner = THIS_MODULE;
0163     mtk_wdt->rcdev.nr_resets = rst_num;
0164     mtk_wdt->rcdev.ops = &toprgu_reset_ops;
0165     mtk_wdt->rcdev.of_node = pdev->dev.of_node;
0166     ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev);
0167     if (ret != 0)
0168         dev_err(&pdev->dev,
0169             "couldn't register wdt reset controller: %d\n", ret);
0170     return ret;
0171 }
0172
0173 static int mtk_wdt_restart(struct watchdog_device *wdt_dev,
0174                unsigned long action, void *data)
0175 {
0176     struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
0177     void __iomem *wdt_base;
0178
0179     wdt_base = mtk_wdt->wdt_base;
0180
0181     while (1) {
0182         writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST);
0183         mdelay(5);
0184     }
0185
0186     return 0;
0187 }
0188
0189 static int mtk_wdt_ping(struct watchdog_device *wdt_dev)
0190 {
0191     struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
0192     void __iomem *wdt_base = mtk_wdt->wdt_base;
0193
0194     iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST);
0195
0196     return 0;
0197 }
0198
0199 static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev,
0200                 unsigned int timeout)
0201 {
0202     struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
0203     void __iomem *wdt_base = mtk_wdt->wdt_base;
0204     u32 reg;
0205
0206     wdt_dev->timeout = timeout;
0207     /*
0208      * In dual mode, irq will be triggered at timeout / 2
0209      * the real timeout occurs at timeout
0210      */
0211     if (wdt_dev->pretimeout)
0212         wdt_dev->pretimeout = timeout / 2;
0213
0214     /*
0215      * One bit is the value of 512 ticks
0216      * The clock has 32 KHz
0217      */
0218     reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6)
0219             | WDT_LENGTH_KEY;
0220     iowrite32(reg, wdt_base + WDT_LENGTH);
0221
0222     mtk_wdt_ping(wdt_dev);
0223
0224     return 0;
0225 }
0226
0227 static void mtk_wdt_init(struct watchdog_device *wdt_dev)
0228 {
0229     struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
0230     void __iomem *wdt_base;
0231
0232     wdt_base = mtk_wdt->wdt_base;
0233
0234     if (readl(wdt_base + WDT_MODE) & WDT_MODE_EN) {
0235         set_bit(WDOG_HW_RUNNING, &wdt_dev->status);
0236         mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
0237     }
0238 }
0239
0240 static int mtk_wdt_stop(struct watchdog_device *wdt_dev)
0241 {
0242     struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
0243     void __iomem *wdt_base = mtk_wdt->wdt_base;
0244     u32 reg;
0245
0246     reg = readl(wdt_base + WDT_MODE);
0247     reg &= ~WDT_MODE_EN;
0248     reg |= WDT_MODE_KEY;
0249     iowrite32(reg, wdt_base + WDT_MODE);
0250
0251     return 0;
0252 }
0253
0254 static int mtk_wdt_start(struct watchdog_device *wdt_dev)
0255 {
0256     u32 reg;
0257     struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
0258     void __iomem *wdt_base = mtk_wdt->wdt_base;
0259     int ret;
0260
0261     ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
0262     if (ret < 0)
0263         return ret;
0264
0265     reg = ioread32(wdt_base + WDT_MODE);
0266     if (wdt_dev->pretimeout)
0267         reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
0268     else
0269         reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
0270     if (mtk_wdt->disable_wdt_extrst)
0271         reg &= ~WDT_MODE_EXRST_EN;
0272     reg |= (WDT_MODE_EN | WDT_MODE_KEY);
0273     iowrite32(reg, wdt_base + WDT_MODE);
0274
0275     return 0;
0276 }
0277
0278 static int mtk_wdt_set_pretimeout(struct watchdog_device *wdd,
0279                   unsigned int timeout)
0280 {
0281     struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd);
0282     void __iomem *wdt_base = mtk_wdt->wdt_base;
0283     u32 reg = ioread32(wdt_base + WDT_MODE);
0284
0285     if (timeout && !wdd->pretimeout) {
0286         wdd->pretimeout = wdd->timeout / 2;
0287         reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
0288     } else if (!timeout && wdd->pretimeout) {
0289         wdd->pretimeout = 0;
0290         reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
0291     } else {
0292         return 0;
0293     }
0294
0295     reg |= WDT_MODE_KEY;
0296     iowrite32(reg, wdt_base + WDT_MODE);
0297
0298     return mtk_wdt_set_timeout(wdd, wdd->timeout);
0299 }
0300
0301 static irqreturn_t mtk_wdt_isr(int irq, void *arg)
0302 {
0303     struct watchdog_device *wdd = arg;
0304
0305     watchdog_notify_pretimeout(wdd);
0306
0307     return IRQ_HANDLED;
0308 }
0309
0310 static const struct watchdog_info mtk_wdt_info = {
0311     .identity   = DRV_NAME,
0312     .options    = WDIOF_SETTIMEOUT |
0313               WDIOF_KEEPALIVEPING |
0314               WDIOF_MAGICCLOSE,
0315 };
0316
0317 static const struct watchdog_info mtk_wdt_pt_info = {
0318     .identity   = DRV_NAME,
0319     .options    = WDIOF_SETTIMEOUT |
0320               WDIOF_PRETIMEOUT |
0321               WDIOF_KEEPALIVEPING |
0322               WDIOF_MAGICCLOSE,
0323 };
0324
0325 static const struct watchdog_ops mtk_wdt_ops = {
0326     .owner      = THIS_MODULE,
0327     .start      = mtk_wdt_start,
0328     .stop       = mtk_wdt_stop,
0329     .ping       = mtk_wdt_ping,
0330     .set_timeout    = mtk_wdt_set_timeout,
0331     .set_pretimeout = mtk_wdt_set_pretimeout,
0332     .restart    = mtk_wdt_restart,
0333 };
0334
0335 static int mtk_wdt_probe(struct platform_device *pdev)
0336 {
0337     struct device *dev = &pdev->dev;
0338     struct mtk_wdt_dev *mtk_wdt;
0339     const struct mtk_wdt_data *wdt_data;
0340     int err, irq;
0341
0342     mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL);
0343     if (!mtk_wdt)
0344         return -ENOMEM;
0345
0346     platform_set_drvdata(pdev, mtk_wdt);
0347
0348     mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
0349     if (IS_ERR(mtk_wdt->wdt_base))
0350         return PTR_ERR(mtk_wdt->wdt_base);
0351
0352     irq = platform_get_irq_optional(pdev, 0);
0353     if (irq > 0) {
0354         err = devm_request_irq(&pdev->dev, irq, mtk_wdt_isr, 0, "wdt_bark",
0355                        &mtk_wdt->wdt_dev);
0356         if (err)
0357             return err;
0358
0359         mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info;
0360         mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2;
0361     } else {
0362         if (irq == -EPROBE_DEFER)
0363             return -EPROBE_DEFER;
0364
0365         mtk_wdt->wdt_dev.info = &mtk_wdt_info;
0366     }
0367
0368     mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;
0369     mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
0370     mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000;
0371     mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
0372     mtk_wdt->wdt_dev.parent = dev;
0373
0374     watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev);
0375     watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);
0376     watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);
0377
0378     watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);
0379
0380     mtk_wdt_init(&mtk_wdt->wdt_dev);
0381
0382     watchdog_stop_on_reboot(&mtk_wdt->wdt_dev);
0383     err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev);
0384     if (unlikely(err))
0385         return err;
0386
0387     dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
0388          mtk_wdt->wdt_dev.timeout, nowayout);
0389
0390     wdt_data = of_device_get_match_data(dev);
0391     if (wdt_data) {
0392         err = toprgu_register_reset_controller(pdev,
0393                                wdt_data->toprgu_sw_rst_num);
0394         if (err)
0395             return err;
0396     }
0397
0398     mtk_wdt->disable_wdt_extrst =
0399         of_property_read_bool(dev->of_node, "mediatek,disable-extrst");
0400
0401     return 0;
0402 }
0403
0404 static int mtk_wdt_suspend(struct device *dev)
0405 {
0406     struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
0407
0408     if (watchdog_active(&mtk_wdt->wdt_dev))
0409         mtk_wdt_stop(&mtk_wdt->wdt_dev);
0410
0411     return 0;
0412 }
0413
0414 static int mtk_wdt_resume(struct device *dev)
0415 {
0416     struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
0417
0418     if (watchdog_active(&mtk_wdt->wdt_dev)) {
0419         mtk_wdt_start(&mtk_wdt->wdt_dev);
0420         mtk_wdt_ping(&mtk_wdt->wdt_dev);
0421     }
0422
0423     return 0;
0424 }
0425
0426 static const struct of_device_id mtk_wdt_dt_ids[] = {
0427     { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
0428     { .compatible = "mediatek,mt6589-wdt" },
0429     { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
0430     { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
0431     { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
0432     { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
0433     { .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data },
0434     { /* sentinel */ }
0435 };
0436 MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
0437
0438 static DEFINE_SIMPLE_DEV_PM_OPS(mtk_wdt_pm_ops,
0439                 mtk_wdt_suspend, mtk_wdt_resume);
0440
0441 static struct platform_driver mtk_wdt_driver = {
0442     .probe      = mtk_wdt_probe,
0443     .driver     = {
0444         .name       = DRV_NAME,
0445         .pm     = pm_sleep_ptr(&mtk_wdt_pm_ops),
0446         .of_match_table = mtk_wdt_dt_ids,
0447     },
0448 };
0449
0450 module_platform_driver(mtk_wdt_driver);
0451
0452 module_param(timeout, uint, 0);
0453 MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
0454
0455 module_param(nowayout, bool, 0);
0456 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
0457             __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
0458
0459 MODULE_LICENSE("GPL");
0460 MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>");
0461 MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver");
0462 MODULE_VERSION(DRV_VERSION);