drivers/watchdog/mt7621_wdt.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Ralink MT7621/MT7628 built-in hardware watchdog timer
0004  *
0005  * Copyright (C) 2014 John Crispin <john@phrozen.org>
0006  *
0007  * This driver was based on: drivers/watchdog/rt2880_wdt.c
0008  */
0009
0010 #include <linux/clk.h>
0011 #include <linux/reset.h>
0012 #include <linux/module.h>
0013 #include <linux/kernel.h>
0014 #include <linux/watchdog.h>
0015 #include <linux/moduleparam.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/mod_devicetable.h>
0018
0019 #include <asm/mach-ralink/ralink_regs.h>
0020
0021 #define SYSC_RSTSTAT            0x38
0022 #define WDT_RST_CAUSE           BIT(1)
0023
0024 #define RALINK_WDT_TIMEOUT      30
0025
0026 #define TIMER_REG_TMRSTAT       0x00
0027 #define TIMER_REG_TMR1LOAD      0x24
0028 #define TIMER_REG_TMR1CTL       0x20
0029
0030 #define TMR1CTL_ENABLE          BIT(7)
0031 #define TMR1CTL_RESTART         BIT(9)
0032 #define TMR1CTL_PRESCALE_SHIFT      16
0033
0034 static void __iomem *mt7621_wdt_base;
0035 static struct reset_control *mt7621_wdt_reset;
0036
0037 static bool nowayout = WATCHDOG_NOWAYOUT;
0038 module_param(nowayout, bool, 0);
0039 MODULE_PARM_DESC(nowayout,
0040          "Watchdog cannot be stopped once started (default="
0041          __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
0042
0043 static inline void rt_wdt_w32(unsigned reg, u32 val)
0044 {
0045     iowrite32(val, mt7621_wdt_base + reg);
0046 }
0047
0048 static inline u32 rt_wdt_r32(unsigned reg)
0049 {
0050     return ioread32(mt7621_wdt_base + reg);
0051 }
0052
0053 static int mt7621_wdt_ping(struct watchdog_device *w)
0054 {
0055     rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
0056
0057     return 0;
0058 }
0059
0060 static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
0061 {
0062     w->timeout = t;
0063     rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000);
0064     mt7621_wdt_ping(w);
0065
0066     return 0;
0067 }
0068
0069 static int mt7621_wdt_start(struct watchdog_device *w)
0070 {
0071     u32 t;
0072
0073     /* set the prescaler to 1ms == 1000us */
0074     rt_wdt_w32(TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);
0075
0076     mt7621_wdt_set_timeout(w, w->timeout);
0077
0078     t = rt_wdt_r32(TIMER_REG_TMR1CTL);
0079     t |= TMR1CTL_ENABLE;
0080     rt_wdt_w32(TIMER_REG_TMR1CTL, t);
0081
0082     return 0;
0083 }
0084
0085 static int mt7621_wdt_stop(struct watchdog_device *w)
0086 {
0087     u32 t;
0088
0089     mt7621_wdt_ping(w);
0090
0091     t = rt_wdt_r32(TIMER_REG_TMR1CTL);
0092     t &= ~TMR1CTL_ENABLE;
0093     rt_wdt_w32(TIMER_REG_TMR1CTL, t);
0094
0095     return 0;
0096 }
0097
0098 static int mt7621_wdt_bootcause(void)
0099 {
0100     if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
0101         return WDIOF_CARDRESET;
0102
0103     return 0;
0104 }
0105
0106 static int mt7621_wdt_is_running(struct watchdog_device *w)
0107 {
0108     return !!(rt_wdt_r32(TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE);
0109 }
0110
0111 static const struct watchdog_info mt7621_wdt_info = {
0112     .identity = "Mediatek Watchdog",
0113     .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
0114 };
0115
0116 static const struct watchdog_ops mt7621_wdt_ops = {
0117     .owner = THIS_MODULE,
0118     .start = mt7621_wdt_start,
0119     .stop = mt7621_wdt_stop,
0120     .ping = mt7621_wdt_ping,
0121     .set_timeout = mt7621_wdt_set_timeout,
0122 };
0123
0124 static struct watchdog_device mt7621_wdt_dev = {
0125     .info = &mt7621_wdt_info,
0126     .ops = &mt7621_wdt_ops,
0127     .min_timeout = 1,
0128     .max_timeout = 0xfffful / 1000,
0129 };
0130
0131 static int mt7621_wdt_probe(struct platform_device *pdev)
0132 {
0133     struct device *dev = &pdev->dev;
0134     mt7621_wdt_base = devm_platform_ioremap_resource(pdev, 0);
0135     if (IS_ERR(mt7621_wdt_base))
0136         return PTR_ERR(mt7621_wdt_base);
0137
0138     mt7621_wdt_reset = devm_reset_control_get_exclusive(dev, NULL);
0139     if (!IS_ERR(mt7621_wdt_reset))
0140         reset_control_deassert(mt7621_wdt_reset);
0141
0142     mt7621_wdt_dev.bootstatus = mt7621_wdt_bootcause();
0143
0144     watchdog_init_timeout(&mt7621_wdt_dev, mt7621_wdt_dev.max_timeout,
0145                   dev);
0146     watchdog_set_nowayout(&mt7621_wdt_dev, nowayout);
0147     if (mt7621_wdt_is_running(&mt7621_wdt_dev)) {
0148         /*
0149          * Make sure to apply timeout from watchdog core, taking
0150          * the prescaler of this driver here into account (the
0151          * boot loader might be using a different prescaler).
0152          *
0153          * To avoid spurious resets because of different scaling,
0154          * we first disable the watchdog, set the new prescaler
0155          * and timeout, and then re-enable the watchdog.
0156          */
0157         mt7621_wdt_stop(&mt7621_wdt_dev);
0158         mt7621_wdt_start(&mt7621_wdt_dev);
0159         set_bit(WDOG_HW_RUNNING, &mt7621_wdt_dev.status);
0160     }
0161
0162     return devm_watchdog_register_device(dev, &mt7621_wdt_dev);
0163 }
0164
0165 static void mt7621_wdt_shutdown(struct platform_device *pdev)
0166 {
0167     mt7621_wdt_stop(&mt7621_wdt_dev);
0168 }
0169
0170 static const struct of_device_id mt7621_wdt_match[] = {
0171     { .compatible = "mediatek,mt7621-wdt" },
0172     {},
0173 };
0174 MODULE_DEVICE_TABLE(of, mt7621_wdt_match);
0175
0176 static struct platform_driver mt7621_wdt_driver = {
0177     .probe      = mt7621_wdt_probe,
0178     .shutdown   = mt7621_wdt_shutdown,
0179     .driver     = {
0180         .name       = KBUILD_MODNAME,
0181         .of_match_table = mt7621_wdt_match,
0182     },
0183 };
0184
0185 module_platform_driver(mt7621_wdt_driver);
0186
0187 MODULE_DESCRIPTION("MediaTek MT762x hardware watchdog driver");
0188 MODULE_AUTHOR("John Crispin <john@phrozen.org");
0189 MODULE_LICENSE("GPL v2");