drivers/watchdog/lpc18xx_wdt.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * NXP LPC18xx Watchdog Timer (WDT)
0004  *
0005  * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com>
0006  *
0007  * Notes
0008  * -----
0009  * The Watchdog consists of a fixed divide-by-4 clock pre-scaler and a 24-bit
0010  * counter which decrements on every clock cycle.
0011  */
0012
0013 #include <linux/clk.h>
0014 #include <linux/io.h>
0015 #include <linux/module.h>
0016 #include <linux/of.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/watchdog.h>
0019
0020 /* Registers */
0021 #define LPC18XX_WDT_MOD         0x00
0022 #define LPC18XX_WDT_MOD_WDEN        BIT(0)
0023 #define LPC18XX_WDT_MOD_WDRESET     BIT(1)
0024
0025 #define LPC18XX_WDT_TC          0x04
0026 #define LPC18XX_WDT_TC_MIN      0xff
0027 #define LPC18XX_WDT_TC_MAX      0xffffff
0028
0029 #define LPC18XX_WDT_FEED        0x08
0030 #define LPC18XX_WDT_FEED_MAGIC1     0xaa
0031 #define LPC18XX_WDT_FEED_MAGIC2     0x55
0032
0033 #define LPC18XX_WDT_TV          0x0c
0034
0035 /* Clock pre-scaler */
0036 #define LPC18XX_WDT_CLK_DIV     4
0037
0038 /* Timeout values in seconds */
0039 #define LPC18XX_WDT_DEF_TIMEOUT     30U
0040
0041 static int heartbeat;
0042 module_param(heartbeat, int, 0);
0043 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds (default="
0044          __MODULE_STRING(LPC18XX_WDT_DEF_TIMEOUT) ")");
0045
0046 static bool nowayout = WATCHDOG_NOWAYOUT;
0047 module_param(nowayout, bool, 0);
0048 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
0049          __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
0050
0051 struct lpc18xx_wdt_dev {
0052     struct watchdog_device  wdt_dev;
0053     struct clk      *reg_clk;
0054     struct clk      *wdt_clk;
0055     unsigned long       clk_rate;
0056     void __iomem        *base;
0057     struct timer_list   timer;
0058     spinlock_t      lock;
0059 };
0060
0061 static int lpc18xx_wdt_feed(struct watchdog_device *wdt_dev)
0062 {
0063     struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
0064     unsigned long flags;
0065
0066     /*
0067      * An abort condition will occur if an interrupt happens during the feed
0068      * sequence.
0069      */
0070     spin_lock_irqsave(&lpc18xx_wdt->lock, flags);
0071     writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
0072     writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
0073     spin_unlock_irqrestore(&lpc18xx_wdt->lock, flags);
0074
0075     return 0;
0076 }
0077
0078 static void lpc18xx_wdt_timer_feed(struct timer_list *t)
0079 {
0080     struct lpc18xx_wdt_dev *lpc18xx_wdt = from_timer(lpc18xx_wdt, t, timer);
0081     struct watchdog_device *wdt_dev = &lpc18xx_wdt->wdt_dev;
0082
0083     lpc18xx_wdt_feed(wdt_dev);
0084
0085     /* Use safe value (1/2 of real timeout) */
0086     mod_timer(&lpc18xx_wdt->timer, jiffies +
0087           msecs_to_jiffies((wdt_dev->timeout * MSEC_PER_SEC) / 2));
0088 }
0089
0090 /*
0091  * Since LPC18xx Watchdog cannot be disabled in hardware, we must keep feeding
0092  * it with a timer until userspace watchdog software takes over.
0093  */
0094 static int lpc18xx_wdt_stop(struct watchdog_device *wdt_dev)
0095 {
0096     struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
0097
0098     lpc18xx_wdt_timer_feed(&lpc18xx_wdt->timer);
0099
0100     return 0;
0101 }
0102
0103 static void __lpc18xx_wdt_set_timeout(struct lpc18xx_wdt_dev *lpc18xx_wdt)
0104 {
0105     unsigned int val;
0106
0107     val = DIV_ROUND_UP(lpc18xx_wdt->wdt_dev.timeout * lpc18xx_wdt->clk_rate,
0108                LPC18XX_WDT_CLK_DIV);
0109     writel(val, lpc18xx_wdt->base + LPC18XX_WDT_TC);
0110 }
0111
0112 static int lpc18xx_wdt_set_timeout(struct watchdog_device *wdt_dev,
0113                    unsigned int new_timeout)
0114 {
0115     struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
0116
0117     lpc18xx_wdt->wdt_dev.timeout = new_timeout;
0118     __lpc18xx_wdt_set_timeout(lpc18xx_wdt);
0119
0120     return 0;
0121 }
0122
0123 static unsigned int lpc18xx_wdt_get_timeleft(struct watchdog_device *wdt_dev)
0124 {
0125     struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
0126     unsigned int val;
0127
0128     val = readl(lpc18xx_wdt->base + LPC18XX_WDT_TV);
0129     return (val * LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate;
0130 }
0131
0132 static int lpc18xx_wdt_start(struct watchdog_device *wdt_dev)
0133 {
0134     struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
0135     unsigned int val;
0136
0137     if (timer_pending(&lpc18xx_wdt->timer))
0138         del_timer(&lpc18xx_wdt->timer);
0139
0140     val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD);
0141     val |= LPC18XX_WDT_MOD_WDEN;
0142     val |= LPC18XX_WDT_MOD_WDRESET;
0143     writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD);
0144
0145     /*
0146      * Setting the WDEN bit in the WDMOD register is not sufficient to
0147      * enable the Watchdog. A valid feed sequence must be completed after
0148      * setting WDEN before the Watchdog is capable of generating a reset.
0149      */
0150     lpc18xx_wdt_feed(wdt_dev);
0151
0152     return 0;
0153 }
0154
0155 static int lpc18xx_wdt_restart(struct watchdog_device *wdt_dev,
0156                    unsigned long action, void *data)
0157 {
0158     struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
0159     unsigned long flags;
0160     int val;
0161
0162     /*
0163      * Incorrect feed sequence causes immediate watchdog reset if enabled.
0164      */
0165     spin_lock_irqsave(&lpc18xx_wdt->lock, flags);
0166
0167     val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD);
0168     val |= LPC18XX_WDT_MOD_WDEN;
0169     val |= LPC18XX_WDT_MOD_WDRESET;
0170     writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD);
0171
0172     writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
0173     writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
0174
0175     writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
0176     writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
0177
0178     spin_unlock_irqrestore(&lpc18xx_wdt->lock, flags);
0179
0180     return 0;
0181 }
0182
0183 static const struct watchdog_info lpc18xx_wdt_info = {
0184     .identity   = "NXP LPC18xx Watchdog",
0185     .options    = WDIOF_SETTIMEOUT |
0186               WDIOF_KEEPALIVEPING |
0187               WDIOF_MAGICCLOSE,
0188 };
0189
0190 static const struct watchdog_ops lpc18xx_wdt_ops = {
0191     .owner      = THIS_MODULE,
0192     .start      = lpc18xx_wdt_start,
0193     .stop       = lpc18xx_wdt_stop,
0194     .ping       = lpc18xx_wdt_feed,
0195     .set_timeout    = lpc18xx_wdt_set_timeout,
0196     .get_timeleft   = lpc18xx_wdt_get_timeleft,
0197     .restart        = lpc18xx_wdt_restart,
0198 };
0199
0200 static void lpc18xx_clk_disable_unprepare(void *data)
0201 {
0202     clk_disable_unprepare(data);
0203 }
0204
0205 static int lpc18xx_wdt_probe(struct platform_device *pdev)
0206 {
0207     struct lpc18xx_wdt_dev *lpc18xx_wdt;
0208     struct device *dev = &pdev->dev;
0209     int ret;
0210
0211     lpc18xx_wdt = devm_kzalloc(dev, sizeof(*lpc18xx_wdt), GFP_KERNEL);
0212     if (!lpc18xx_wdt)
0213         return -ENOMEM;
0214
0215     lpc18xx_wdt->base = devm_platform_ioremap_resource(pdev, 0);
0216     if (IS_ERR(lpc18xx_wdt->base))
0217         return PTR_ERR(lpc18xx_wdt->base);
0218
0219     lpc18xx_wdt->reg_clk = devm_clk_get(dev, "reg");
0220     if (IS_ERR(lpc18xx_wdt->reg_clk)) {
0221         dev_err(dev, "failed to get the reg clock\n");
0222         return PTR_ERR(lpc18xx_wdt->reg_clk);
0223     }
0224
0225     lpc18xx_wdt->wdt_clk = devm_clk_get(dev, "wdtclk");
0226     if (IS_ERR(lpc18xx_wdt->wdt_clk)) {
0227         dev_err(dev, "failed to get the wdt clock\n");
0228         return PTR_ERR(lpc18xx_wdt->wdt_clk);
0229     }
0230
0231     ret = clk_prepare_enable(lpc18xx_wdt->reg_clk);
0232     if (ret) {
0233         dev_err(dev, "could not prepare or enable sys clock\n");
0234         return ret;
0235     }
0236     ret = devm_add_action_or_reset(dev, lpc18xx_clk_disable_unprepare,
0237                        lpc18xx_wdt->reg_clk);
0238     if (ret)
0239         return ret;
0240
0241     ret = clk_prepare_enable(lpc18xx_wdt->wdt_clk);
0242     if (ret) {
0243         dev_err(dev, "could not prepare or enable wdt clock\n");
0244         return ret;
0245     }
0246     ret = devm_add_action_or_reset(dev, lpc18xx_clk_disable_unprepare,
0247                        lpc18xx_wdt->wdt_clk);
0248     if (ret)
0249         return ret;
0250
0251     /* We use the clock rate to calculate timeouts */
0252     lpc18xx_wdt->clk_rate = clk_get_rate(lpc18xx_wdt->wdt_clk);
0253     if (lpc18xx_wdt->clk_rate == 0) {
0254         dev_err(dev, "failed to get clock rate\n");
0255         return -EINVAL;
0256     }
0257
0258     lpc18xx_wdt->wdt_dev.info = &lpc18xx_wdt_info;
0259     lpc18xx_wdt->wdt_dev.ops = &lpc18xx_wdt_ops;
0260
0261     lpc18xx_wdt->wdt_dev.min_timeout = DIV_ROUND_UP(LPC18XX_WDT_TC_MIN *
0262                 LPC18XX_WDT_CLK_DIV, lpc18xx_wdt->clk_rate);
0263
0264     lpc18xx_wdt->wdt_dev.max_timeout = (LPC18XX_WDT_TC_MAX *
0265                 LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate;
0266
0267     lpc18xx_wdt->wdt_dev.timeout = min(lpc18xx_wdt->wdt_dev.max_timeout,
0268                        LPC18XX_WDT_DEF_TIMEOUT);
0269
0270     spin_lock_init(&lpc18xx_wdt->lock);
0271
0272     lpc18xx_wdt->wdt_dev.parent = dev;
0273     watchdog_set_drvdata(&lpc18xx_wdt->wdt_dev, lpc18xx_wdt);
0274
0275     watchdog_init_timeout(&lpc18xx_wdt->wdt_dev, heartbeat, dev);
0276
0277     __lpc18xx_wdt_set_timeout(lpc18xx_wdt);
0278
0279     timer_setup(&lpc18xx_wdt->timer, lpc18xx_wdt_timer_feed, 0);
0280
0281     watchdog_set_nowayout(&lpc18xx_wdt->wdt_dev, nowayout);
0282     watchdog_set_restart_priority(&lpc18xx_wdt->wdt_dev, 128);
0283
0284     platform_set_drvdata(pdev, lpc18xx_wdt);
0285
0286     watchdog_stop_on_reboot(&lpc18xx_wdt->wdt_dev);
0287     return devm_watchdog_register_device(dev, &lpc18xx_wdt->wdt_dev);
0288 }
0289
0290 static int lpc18xx_wdt_remove(struct platform_device *pdev)
0291 {
0292     struct lpc18xx_wdt_dev *lpc18xx_wdt = platform_get_drvdata(pdev);
0293
0294     dev_warn(&pdev->dev, "I quit now, hardware will probably reboot!\n");
0295     del_timer_sync(&lpc18xx_wdt->timer);
0296
0297     return 0;
0298 }
0299
0300 static const struct of_device_id lpc18xx_wdt_match[] = {
0301     { .compatible = "nxp,lpc1850-wwdt" },
0302     {}
0303 };
0304 MODULE_DEVICE_TABLE(of, lpc18xx_wdt_match);
0305
0306 static struct platform_driver lpc18xx_wdt_driver = {
0307     .driver = {
0308         .name = "lpc18xx-wdt",
0309         .of_match_table = lpc18xx_wdt_match,
0310     },
0311     .probe = lpc18xx_wdt_probe,
0312     .remove = lpc18xx_wdt_remove,
0313 };
0314 module_platform_driver(lpc18xx_wdt_driver);
0315
0316 MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>");
0317 MODULE_DESCRIPTION("NXP LPC18xx Watchdog Timer Driver");
0318 MODULE_LICENSE("GPL v2");