drivers/watchdog/keembay_wdt.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Watchdog driver for Intel Keem Bay non-secure watchdog.
0004  *
0005  * Copyright (C) 2020 Intel Corporation
0006  */
0007
0008 #include <linux/arm-smccc.h>
0009 #include <linux/bits.h>
0010 #include <linux/clk.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/io.h>
0013 #include <linux/limits.h>
0014 #include <linux/module.h>
0015 #include <linux/mod_devicetable.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/reboot.h>
0018 #include <linux/watchdog.h>
0019
0020 /* Non-secure watchdog register offsets */
0021 #define TIM_WATCHDOG        0x0
0022 #define TIM_WATCHDOG_INT_THRES  0x4
0023 #define TIM_WDOG_EN     0x8
0024 #define TIM_SAFE        0xc
0025
0026 #define WDT_TH_INT_MASK     BIT(8)
0027 #define WDT_TO_INT_MASK     BIT(9)
0028 #define WDT_INT_CLEAR_SMC   0x8200ff18
0029
0030 #define WDT_UNLOCK      0xf1d0dead
0031 #define WDT_DISABLE     0x0
0032 #define WDT_ENABLE      0x1
0033
0034 #define WDT_LOAD_MAX        U32_MAX
0035 #define WDT_LOAD_MIN        1
0036
0037 #define WDT_TIMEOUT     5
0038 #define WDT_PRETIMEOUT      4
0039
0040 static unsigned int timeout = WDT_TIMEOUT;
0041 module_param(timeout, int, 0);
0042 MODULE_PARM_DESC(timeout, "Watchdog timeout period in seconds (default = "
0043          __MODULE_STRING(WDT_TIMEOUT) ")");
0044
0045 static bool nowayout = WATCHDOG_NOWAYOUT;
0046 module_param(nowayout, bool, 0);
0047 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default = "
0048          __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
0049
0050 struct keembay_wdt {
0051     struct watchdog_device  wdd;
0052     struct clk      *clk;
0053     unsigned int        rate;
0054     int         to_irq;
0055     int         th_irq;
0056     void __iomem        *base;
0057 };
0058
0059 static inline u32 keembay_wdt_readl(struct keembay_wdt *wdt, u32 offset)
0060 {
0061     return readl(wdt->base + offset);
0062 }
0063
0064 static inline void keembay_wdt_writel(struct keembay_wdt *wdt, u32 offset, u32 val)
0065 {
0066     writel(WDT_UNLOCK, wdt->base + TIM_SAFE);
0067     writel(val, wdt->base + offset);
0068 }
0069
0070 static void keembay_wdt_set_timeout_reg(struct watchdog_device *wdog)
0071 {
0072     struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
0073
0074     keembay_wdt_writel(wdt, TIM_WATCHDOG, wdog->timeout * wdt->rate);
0075 }
0076
0077 static void keembay_wdt_set_pretimeout_reg(struct watchdog_device *wdog)
0078 {
0079     struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
0080     u32 th_val = 0;
0081
0082     if (wdog->pretimeout)
0083         th_val = wdog->timeout - wdog->pretimeout;
0084
0085     keembay_wdt_writel(wdt, TIM_WATCHDOG_INT_THRES, th_val * wdt->rate);
0086 }
0087
0088 static int keembay_wdt_start(struct watchdog_device *wdog)
0089 {
0090     struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
0091
0092     keembay_wdt_writel(wdt, TIM_WDOG_EN, WDT_ENABLE);
0093
0094     return 0;
0095 }
0096
0097 static int keembay_wdt_stop(struct watchdog_device *wdog)
0098 {
0099     struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
0100
0101     keembay_wdt_writel(wdt, TIM_WDOG_EN, WDT_DISABLE);
0102
0103     return 0;
0104 }
0105
0106 static int keembay_wdt_ping(struct watchdog_device *wdog)
0107 {
0108     keembay_wdt_set_timeout_reg(wdog);
0109
0110     return 0;
0111 }
0112
0113 static int keembay_wdt_set_timeout(struct watchdog_device *wdog, u32 t)
0114 {
0115     wdog->timeout = t;
0116     keembay_wdt_set_timeout_reg(wdog);
0117     keembay_wdt_set_pretimeout_reg(wdog);
0118
0119     return 0;
0120 }
0121
0122 static int keembay_wdt_set_pretimeout(struct watchdog_device *wdog, u32 t)
0123 {
0124     if (t > wdog->timeout)
0125         return -EINVAL;
0126
0127     wdog->pretimeout = t;
0128     keembay_wdt_set_pretimeout_reg(wdog);
0129
0130     return 0;
0131 }
0132
0133 static unsigned int keembay_wdt_get_timeleft(struct watchdog_device *wdog)
0134 {
0135     struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
0136
0137     return keembay_wdt_readl(wdt, TIM_WATCHDOG) / wdt->rate;
0138 }
0139
0140 /*
0141  * SMC call is used to clear the interrupt bits, because the TIM_GEN_CONFIG
0142  * register is in the secure bank.
0143  */
0144 static irqreturn_t keembay_wdt_to_isr(int irq, void *dev_id)
0145 {
0146     struct keembay_wdt *wdt = dev_id;
0147     struct arm_smccc_res res;
0148
0149     arm_smccc_smc(WDT_INT_CLEAR_SMC, WDT_TO_INT_MASK, 0, 0, 0, 0, 0, 0, &res);
0150     dev_crit(wdt->wdd.parent, "Intel Keem Bay non-secure wdt timeout.\n");
0151     emergency_restart();
0152
0153     return IRQ_HANDLED;
0154 }
0155
0156 static irqreturn_t keembay_wdt_th_isr(int irq, void *dev_id)
0157 {
0158     struct keembay_wdt *wdt = dev_id;
0159     struct arm_smccc_res res;
0160
0161     keembay_wdt_set_pretimeout(&wdt->wdd, 0x0);
0162
0163     arm_smccc_smc(WDT_INT_CLEAR_SMC, WDT_TH_INT_MASK, 0, 0, 0, 0, 0, 0, &res);
0164     dev_crit(wdt->wdd.parent, "Intel Keem Bay non-secure wdt pre-timeout.\n");
0165     watchdog_notify_pretimeout(&wdt->wdd);
0166
0167     return IRQ_HANDLED;
0168 }
0169
0170 static const struct watchdog_info keembay_wdt_info = {
0171     .identity   = "Intel Keem Bay Watchdog Timer",
0172     .options    = WDIOF_SETTIMEOUT |
0173               WDIOF_PRETIMEOUT |
0174               WDIOF_MAGICCLOSE |
0175               WDIOF_KEEPALIVEPING,
0176 };
0177
0178 static const struct watchdog_ops keembay_wdt_ops = {
0179     .owner      = THIS_MODULE,
0180     .start      = keembay_wdt_start,
0181     .stop       = keembay_wdt_stop,
0182     .ping       = keembay_wdt_ping,
0183     .set_timeout    = keembay_wdt_set_timeout,
0184     .set_pretimeout = keembay_wdt_set_pretimeout,
0185     .get_timeleft   = keembay_wdt_get_timeleft,
0186 };
0187
0188 static int keembay_wdt_probe(struct platform_device *pdev)
0189 {
0190     struct device *dev = &pdev->dev;
0191     struct keembay_wdt *wdt;
0192     int ret;
0193
0194     wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
0195     if (!wdt)
0196         return -ENOMEM;
0197
0198     wdt->base = devm_platform_ioremap_resource(pdev, 0);
0199     if (IS_ERR(wdt->base))
0200         return PTR_ERR(wdt->base);
0201
0202     /* we do not need to enable the clock as it is enabled by default */
0203     wdt->clk = devm_clk_get(dev, NULL);
0204     if (IS_ERR(wdt->clk))
0205         return dev_err_probe(dev, PTR_ERR(wdt->clk), "Failed to get clock\n");
0206
0207     wdt->rate = clk_get_rate(wdt->clk);
0208     if (!wdt->rate)
0209         return dev_err_probe(dev, -EINVAL, "Failed to get clock rate\n");
0210
0211     wdt->th_irq = platform_get_irq_byname(pdev, "threshold");
0212     if (wdt->th_irq < 0)
0213         return dev_err_probe(dev, wdt->th_irq, "Failed to get IRQ for threshold\n");
0214
0215     ret = devm_request_irq(dev, wdt->th_irq, keembay_wdt_th_isr, 0,
0216                    "keembay-wdt", wdt);
0217     if (ret)
0218         return dev_err_probe(dev, ret, "Failed to request IRQ for threshold\n");
0219
0220     wdt->to_irq = platform_get_irq_byname(pdev, "timeout");
0221     if (wdt->to_irq < 0)
0222         return dev_err_probe(dev, wdt->to_irq, "Failed to get IRQ for timeout\n");
0223
0224     ret = devm_request_irq(dev, wdt->to_irq, keembay_wdt_to_isr, 0,
0225                    "keembay-wdt", wdt);
0226     if (ret)
0227         return dev_err_probe(dev, ret, "Failed to request IRQ for timeout\n");
0228
0229     wdt->wdd.parent     = dev;
0230     wdt->wdd.info       = &keembay_wdt_info;
0231     wdt->wdd.ops        = &keembay_wdt_ops;
0232     wdt->wdd.min_timeout    = WDT_LOAD_MIN;
0233     wdt->wdd.max_timeout    = WDT_LOAD_MAX / wdt->rate;
0234     wdt->wdd.timeout    = WDT_TIMEOUT;
0235     wdt->wdd.pretimeout = WDT_PRETIMEOUT;
0236
0237     watchdog_set_drvdata(&wdt->wdd, wdt);
0238     watchdog_set_nowayout(&wdt->wdd, nowayout);
0239     watchdog_init_timeout(&wdt->wdd, timeout, dev);
0240     keembay_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);
0241     keembay_wdt_set_pretimeout(&wdt->wdd, wdt->wdd.pretimeout);
0242
0243     ret = devm_watchdog_register_device(dev, &wdt->wdd);
0244     if (ret)
0245         return dev_err_probe(dev, ret, "Failed to register watchdog device.\n");
0246
0247     platform_set_drvdata(pdev, wdt);
0248     dev_info(dev, "Initial timeout %d sec%s.\n",
0249          wdt->wdd.timeout, nowayout ? ", nowayout" : "");
0250
0251     return 0;
0252 }
0253
0254 static int __maybe_unused keembay_wdt_suspend(struct device *dev)
0255 {
0256     struct keembay_wdt *wdt = dev_get_drvdata(dev);
0257
0258     if (watchdog_active(&wdt->wdd))
0259         return keembay_wdt_stop(&wdt->wdd);
0260
0261     return 0;
0262 }
0263
0264 static int __maybe_unused keembay_wdt_resume(struct device *dev)
0265 {
0266     struct keembay_wdt *wdt = dev_get_drvdata(dev);
0267
0268     if (watchdog_active(&wdt->wdd))
0269         return keembay_wdt_start(&wdt->wdd);
0270
0271     return 0;
0272 }
0273
0274 static SIMPLE_DEV_PM_OPS(keembay_wdt_pm_ops, keembay_wdt_suspend,
0275              keembay_wdt_resume);
0276
0277 static const struct of_device_id keembay_wdt_match[] = {
0278     { .compatible = "intel,keembay-wdt" },
0279     { }
0280 };
0281 MODULE_DEVICE_TABLE(of, keembay_wdt_match);
0282
0283 static struct platform_driver keembay_wdt_driver = {
0284     .probe  = keembay_wdt_probe,
0285     .driver = {
0286         .name       = "keembay_wdt",
0287         .of_match_table = keembay_wdt_match,
0288         .pm     = &keembay_wdt_pm_ops,
0289     },
0290 };
0291
0292 module_platform_driver(keembay_wdt_driver);
0293
0294 MODULE_DESCRIPTION("Intel Keem Bay SoC watchdog driver");
0295 MODULE_AUTHOR("Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com");
0296 MODULE_LICENSE("GPL v2");