drivers/watchdog/ibmasr.c

0001 /*
0002  * IBM Automatic Server Restart driver.
0003  *
0004  * Copyright (c) 2005 Andrey Panin <pazke@donpac.ru>
0005  *
0006  * Based on driver written by Pete Reynolds.
0007  * Copyright (c) IBM Corporation, 1998-2004.
0008  *
0009  * This software may be used and distributed according to the terms
0010  * of the GNU Public License, incorporated herein by reference.
0011  */
0012
0013 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0014
0015 #include <linux/fs.h>
0016 #include <linux/kernel.h>
0017 #include <linux/module.h>
0018 #include <linux/pci.h>
0019 #include <linux/timer.h>
0020 #include <linux/miscdevice.h>
0021 #include <linux/watchdog.h>
0022 #include <linux/dmi.h>
0023 #include <linux/io.h>
0024 #include <linux/uaccess.h>
0025
0026
0027 enum {
0028     ASMTYPE_UNKNOWN,
0029     ASMTYPE_TOPAZ,
0030     ASMTYPE_JASPER,
0031     ASMTYPE_PEARL,
0032     ASMTYPE_JUNIPER,
0033     ASMTYPE_SPRUCE,
0034 };
0035
0036 #define TOPAZ_ASR_REG_OFFSET    4
0037 #define TOPAZ_ASR_TOGGLE    0x40
0038 #define TOPAZ_ASR_DISABLE   0x80
0039
0040 /* PEARL ASR S/W REGISTER SUPERIO PORT ADDRESSES */
0041 #define PEARL_BASE  0xe04
0042 #define PEARL_WRITE 0xe06
0043 #define PEARL_READ  0xe07
0044
0045 #define PEARL_ASR_DISABLE_MASK  0x80    /* bit 7: disable = 1, enable = 0 */
0046 #define PEARL_ASR_TOGGLE_MASK   0x40    /* bit 6: 0, then 1, then 0 */
0047
0048 /* JASPER OFFSET FROM SIO BASE ADDR TO ASR S/W REGISTERS. */
0049 #define JASPER_ASR_REG_OFFSET   0x38
0050
0051 #define JASPER_ASR_DISABLE_MASK 0x01    /* bit 0: disable = 1, enable = 0 */
0052 #define JASPER_ASR_TOGGLE_MASK  0x02    /* bit 1: 0, then 1, then 0 */
0053
0054 #define JUNIPER_BASE_ADDRESS    0x54b   /* Base address of Juniper ASR */
0055 #define JUNIPER_ASR_DISABLE_MASK 0x01   /* bit 0: disable = 1 enable = 0 */
0056 #define JUNIPER_ASR_TOGGLE_MASK 0x02    /* bit 1: 0, then 1, then 0 */
0057
0058 #define SPRUCE_BASE_ADDRESS 0x118e  /* Base address of Spruce ASR */
0059 #define SPRUCE_ASR_DISABLE_MASK 0x01    /* bit 1: disable = 1 enable = 0 */
0060 #define SPRUCE_ASR_TOGGLE_MASK  0x02    /* bit 0: 0, then 1, then 0 */
0061
0062
0063 static bool nowayout = WATCHDOG_NOWAYOUT;
0064
0065 static unsigned long asr_is_open;
0066 static char asr_expect_close;
0067
0068 static unsigned int asr_type, asr_base, asr_length;
0069 static unsigned int asr_read_addr, asr_write_addr;
0070 static unsigned char asr_toggle_mask, asr_disable_mask;
0071 static DEFINE_SPINLOCK(asr_lock);
0072
0073 static void __asr_toggle(void)
0074 {
0075     unsigned char reg;
0076
0077     reg = inb(asr_read_addr);
0078
0079     outb(reg & ~asr_toggle_mask, asr_write_addr);
0080     reg = inb(asr_read_addr);
0081
0082     outb(reg | asr_toggle_mask, asr_write_addr);
0083     reg = inb(asr_read_addr);
0084
0085     outb(reg & ~asr_toggle_mask, asr_write_addr);
0086     reg = inb(asr_read_addr);
0087 }
0088
0089 static void asr_toggle(void)
0090 {
0091     spin_lock(&asr_lock);
0092     __asr_toggle();
0093     spin_unlock(&asr_lock);
0094 }
0095
0096 static void asr_enable(void)
0097 {
0098     unsigned char reg;
0099
0100     spin_lock(&asr_lock);
0101     if (asr_type == ASMTYPE_TOPAZ) {
0102         /* asr_write_addr == asr_read_addr */
0103         reg = inb(asr_read_addr);
0104         outb(reg & ~(TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE),
0105              asr_read_addr);
0106     } else {
0107         /*
0108          * First make sure the hardware timer is reset by toggling
0109          * ASR hardware timer line.
0110          */
0111         __asr_toggle();
0112
0113         reg = inb(asr_read_addr);
0114         outb(reg & ~asr_disable_mask, asr_write_addr);
0115     }
0116     reg = inb(asr_read_addr);
0117     spin_unlock(&asr_lock);
0118 }
0119
0120 static void asr_disable(void)
0121 {
0122     unsigned char reg;
0123
0124     spin_lock(&asr_lock);
0125     reg = inb(asr_read_addr);
0126
0127     if (asr_type == ASMTYPE_TOPAZ)
0128         /* asr_write_addr == asr_read_addr */
0129         outb(reg | TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE,
0130              asr_read_addr);
0131     else {
0132         outb(reg | asr_toggle_mask, asr_write_addr);
0133         reg = inb(asr_read_addr);
0134
0135         outb(reg | asr_disable_mask, asr_write_addr);
0136     }
0137     reg = inb(asr_read_addr);
0138     spin_unlock(&asr_lock);
0139 }
0140
0141 static int __init asr_get_base_address(void)
0142 {
0143     unsigned char low, high;
0144     const char *type = "";
0145
0146     asr_length = 1;
0147
0148     switch (asr_type) {
0149     case ASMTYPE_TOPAZ:
0150         /* SELECT SuperIO CHIP FOR QUERYING
0151            (WRITE 0x07 TO BOTH 0x2E and 0x2F) */
0152         outb(0x07, 0x2e);
0153         outb(0x07, 0x2f);
0154
0155         /* SELECT AND READ THE HIGH-NIBBLE OF THE GPIO BASE ADDRESS */
0156         outb(0x60, 0x2e);
0157         high = inb(0x2f);
0158
0159         /* SELECT AND READ THE LOW-NIBBLE OF THE GPIO BASE ADDRESS */
0160         outb(0x61, 0x2e);
0161         low = inb(0x2f);
0162
0163         asr_base = (high << 16) | low;
0164         asr_read_addr = asr_write_addr =
0165             asr_base + TOPAZ_ASR_REG_OFFSET;
0166         asr_length = 5;
0167
0168         break;
0169
0170     case ASMTYPE_JASPER:
0171         type = "Jaspers ";
0172 #if 0
0173         u32 r;
0174         /* Suggested fix */
0175         pdev = pci_get_bus_and_slot(0, DEVFN(0x1f, 0));
0176         if (pdev == NULL)
0177             return -ENODEV;
0178         pci_read_config_dword(pdev, 0x58, &r);
0179         asr_base = r & 0xFFFE;
0180         pci_dev_put(pdev);
0181 #else
0182         /* FIXME: need to use pci_config_lock here,
0183            but it's not exported */
0184
0185 /*      spin_lock_irqsave(&pci_config_lock, flags);*/
0186
0187         /* Select the SuperIO chip in the PCI I/O port register */
0188         outl(0x8000f858, 0xcf8);
0189
0190         /* BUS 0, Slot 1F, fnc 0, offset 58 */
0191
0192         /*
0193          * Read the base address for the SuperIO chip.
0194          * Only the lower 16 bits are valid, but the address is word
0195          * aligned so the last bit must be masked off.
0196          */
0197         asr_base = inl(0xcfc) & 0xfffe;
0198
0199 /*      spin_unlock_irqrestore(&pci_config_lock, flags);*/
0200 #endif
0201         asr_read_addr = asr_write_addr =
0202             asr_base + JASPER_ASR_REG_OFFSET;
0203         asr_toggle_mask = JASPER_ASR_TOGGLE_MASK;
0204         asr_disable_mask = JASPER_ASR_DISABLE_MASK;
0205         asr_length = JASPER_ASR_REG_OFFSET + 1;
0206
0207         break;
0208
0209     case ASMTYPE_PEARL:
0210         type = "Pearls ";
0211         asr_base = PEARL_BASE;
0212         asr_read_addr = PEARL_READ;
0213         asr_write_addr = PEARL_WRITE;
0214         asr_toggle_mask = PEARL_ASR_TOGGLE_MASK;
0215         asr_disable_mask = PEARL_ASR_DISABLE_MASK;
0216         asr_length = 4;
0217         break;
0218
0219     case ASMTYPE_JUNIPER:
0220         type = "Junipers ";
0221         asr_base = JUNIPER_BASE_ADDRESS;
0222         asr_read_addr = asr_write_addr = asr_base;
0223         asr_toggle_mask = JUNIPER_ASR_TOGGLE_MASK;
0224         asr_disable_mask = JUNIPER_ASR_DISABLE_MASK;
0225         break;
0226
0227     case ASMTYPE_SPRUCE:
0228         type = "Spruce's ";
0229         asr_base = SPRUCE_BASE_ADDRESS;
0230         asr_read_addr = asr_write_addr = asr_base;
0231         asr_toggle_mask = SPRUCE_ASR_TOGGLE_MASK;
0232         asr_disable_mask = SPRUCE_ASR_DISABLE_MASK;
0233         break;
0234     }
0235
0236     if (!request_region(asr_base, asr_length, "ibmasr")) {
0237         pr_err("address %#x already in use\n", asr_base);
0238         return -EBUSY;
0239     }
0240
0241     pr_info("found %sASR @ addr %#x\n", type, asr_base);
0242
0243     return 0;
0244 }
0245
0246
0247 static ssize_t asr_write(struct file *file, const char __user *buf,
0248              size_t count, loff_t *ppos)
0249 {
0250     if (count) {
0251         if (!nowayout) {
0252             size_t i;
0253
0254             /* In case it was set long ago */
0255             asr_expect_close = 0;
0256
0257             for (i = 0; i != count; i++) {
0258                 char c;
0259                 if (get_user(c, buf + i))
0260                     return -EFAULT;
0261                 if (c == 'V')
0262                     asr_expect_close = 42;
0263             }
0264         }
0265         asr_toggle();
0266     }
0267     return count;
0268 }
0269
0270 static long asr_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
0271 {
0272     static const struct watchdog_info ident = {
0273         .options =  WDIOF_KEEPALIVEPING |
0274                 WDIOF_MAGICCLOSE,
0275         .identity = "IBM ASR",
0276     };
0277     void __user *argp = (void __user *)arg;
0278     int __user *p = argp;
0279     int heartbeat;
0280
0281     switch (cmd) {
0282     case WDIOC_GETSUPPORT:
0283         return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
0284     case WDIOC_GETSTATUS:
0285     case WDIOC_GETBOOTSTATUS:
0286         return put_user(0, p);
0287     case WDIOC_SETOPTIONS:
0288     {
0289         int new_options, retval = -EINVAL;
0290         if (get_user(new_options, p))
0291             return -EFAULT;
0292         if (new_options & WDIOS_DISABLECARD) {
0293             asr_disable();
0294             retval = 0;
0295         }
0296         if (new_options & WDIOS_ENABLECARD) {
0297             asr_enable();
0298             asr_toggle();
0299             retval = 0;
0300         }
0301         return retval;
0302     }
0303     case WDIOC_KEEPALIVE:
0304         asr_toggle();
0305         return 0;
0306     /*
0307      * The hardware has a fixed timeout value, so no WDIOC_SETTIMEOUT
0308      * and WDIOC_GETTIMEOUT always returns 256.
0309      */
0310     case WDIOC_GETTIMEOUT:
0311         heartbeat = 256;
0312         return put_user(heartbeat, p);
0313     default:
0314         return -ENOTTY;
0315     }
0316 }
0317
0318 static int asr_open(struct inode *inode, struct file *file)
0319 {
0320     if (test_and_set_bit(0, &asr_is_open))
0321         return -EBUSY;
0322
0323     asr_toggle();
0324     asr_enable();
0325
0326     return stream_open(inode, file);
0327 }
0328
0329 static int asr_release(struct inode *inode, struct file *file)
0330 {
0331     if (asr_expect_close == 42)
0332         asr_disable();
0333     else {
0334         pr_crit("unexpected close, not stopping watchdog!\n");
0335         asr_toggle();
0336     }
0337     clear_bit(0, &asr_is_open);
0338     asr_expect_close = 0;
0339     return 0;
0340 }
0341
0342 static const struct file_operations asr_fops = {
0343     .owner =        THIS_MODULE,
0344     .llseek =       no_llseek,
0345     .write =        asr_write,
0346     .unlocked_ioctl =   asr_ioctl,
0347     .compat_ioctl =     compat_ptr_ioctl,
0348     .open =         asr_open,
0349     .release =      asr_release,
0350 };
0351
0352 static struct miscdevice asr_miscdev = {
0353     .minor =    WATCHDOG_MINOR,
0354     .name =     "watchdog",
0355     .fops =     &asr_fops,
0356 };
0357
0358
0359 struct ibmasr_id {
0360     const char *desc;
0361     int type;
0362 };
0363
0364 static struct ibmasr_id ibmasr_id_table[] __initdata = {
0365     { "IBM Automatic Server Restart - eserver xSeries 220", ASMTYPE_TOPAZ },
0366     { "IBM Automatic Server Restart - Machine Type 8673", ASMTYPE_PEARL },
0367     { "IBM Automatic Server Restart - Machine Type 8480", ASMTYPE_JASPER },
0368     { "IBM Automatic Server Restart - Machine Type 8482", ASMTYPE_JUNIPER },
0369     { "IBM Automatic Server Restart - Machine Type 8648", ASMTYPE_SPRUCE },
0370     { NULL }
0371 };
0372
0373 static int __init ibmasr_init(void)
0374 {
0375     struct ibmasr_id *id;
0376     int rc;
0377
0378     for (id = ibmasr_id_table; id->desc; id++) {
0379         if (dmi_find_device(DMI_DEV_TYPE_OTHER, id->desc, NULL)) {
0380             asr_type = id->type;
0381             break;
0382         }
0383     }
0384
0385     if (!asr_type)
0386         return -ENODEV;
0387
0388     rc = asr_get_base_address();
0389     if (rc)
0390         return rc;
0391
0392     rc = misc_register(&asr_miscdev);
0393     if (rc < 0) {
0394         release_region(asr_base, asr_length);
0395         pr_err("failed to register misc device\n");
0396         return rc;
0397     }
0398
0399     return 0;
0400 }
0401
0402 static void __exit ibmasr_exit(void)
0403 {
0404     if (!nowayout)
0405         asr_disable();
0406
0407     misc_deregister(&asr_miscdev);
0408
0409     release_region(asr_base, asr_length);
0410 }
0411
0412 module_init(ibmasr_init);
0413 module_exit(ibmasr_exit);
0414
0415 module_param(nowayout, bool, 0);
0416 MODULE_PARM_DESC(nowayout,
0417     "Watchdog cannot be stopped once started (default="
0418                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
0419
0420 MODULE_DESCRIPTION("IBM Automatic Server Restart driver");
0421 MODULE_AUTHOR("Andrey Panin");
0422 MODULE_LICENSE("GPL");