drivers/watchdog/iTCO_wdt.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  *  intel TCO Watchdog Driver
0004  *
0005  *  (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
0006  *
0007  *  Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
0008  *  provide warranty for any of this software. This material is
0009  *  provided "AS-IS" and at no charge.
0010  *
0011  *  The TCO watchdog is implemented in the following I/O controller hubs:
0012  *  (See the intel documentation on http://developer.intel.com.)
0013  *  document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
0014  *  document number 290687-002, 298242-027: 82801BA (ICH2)
0015  *  document number 290733-003, 290739-013: 82801CA (ICH3-S)
0016  *  document number 290716-001, 290718-007: 82801CAM (ICH3-M)
0017  *  document number 290744-001, 290745-025: 82801DB (ICH4)
0018  *  document number 252337-001, 252663-008: 82801DBM (ICH4-M)
0019  *  document number 273599-001, 273645-002: 82801E (C-ICH)
0020  *  document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
0021  *  document number 300641-004, 300884-013: 6300ESB
0022  *  document number 301473-002, 301474-026: 82801F (ICH6)
0023  *  document number 313082-001, 313075-006: 631xESB, 632xESB
0024  *  document number 307013-003, 307014-024: 82801G (ICH7)
0025  *  document number 322896-001, 322897-001: NM10
0026  *  document number 313056-003, 313057-017: 82801H (ICH8)
0027  *  document number 316972-004, 316973-012: 82801I (ICH9)
0028  *  document number 319973-002, 319974-002: 82801J (ICH10)
0029  *  document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
0030  *  document number 320066-003, 320257-008: EP80597 (IICH)
0031  *  document number 324645-001, 324646-001: Cougar Point (CPT)
0032  *  document number TBD                   : Patsburg (PBG)
0033  *  document number TBD                   : DH89xxCC
0034  *  document number TBD                   : Panther Point
0035  *  document number TBD                   : Lynx Point
0036  *  document number TBD                   : Lynx Point-LP
0037  */
0038
0039 /*
0040  *  Includes, defines, variables, module parameters, ...
0041  */
0042
0043 /* Module and version information */
0044 #define DRV_NAME    "iTCO_wdt"
0045 #define DRV_VERSION "1.11"
0046
0047 /* Includes */
0048 #include <linux/acpi.h>         /* For ACPI support */
0049 #include <linux/bits.h>         /* For BIT() */
0050 #include <linux/module.h>       /* For module specific items */
0051 #include <linux/moduleparam.h>      /* For new moduleparam's */
0052 #include <linux/types.h>        /* For standard types (like size_t) */
0053 #include <linux/errno.h>        /* For the -ENODEV/... values */
0054 #include <linux/kernel.h>       /* For printk/panic/... */
0055 #include <linux/watchdog.h>     /* For the watchdog specific items */
0056 #include <linux/init.h>         /* For __init/__exit/... */
0057 #include <linux/fs.h>           /* For file operations */
0058 #include <linux/platform_device.h>  /* For platform_driver framework */
0059 #include <linux/pci.h>          /* For pci functions */
0060 #include <linux/ioport.h>       /* For io-port access */
0061 #include <linux/spinlock.h>     /* For spin_lock/spin_unlock/... */
0062 #include <linux/uaccess.h>      /* For copy_to_user/put_user/... */
0063 #include <linux/io.h>           /* For inb/outb/... */
0064 #include <linux/platform_data/itco_wdt.h>
0065 #include <linux/mfd/intel_pmc_bxt.h>
0066
0067 #include "iTCO_vendor.h"
0068
0069 /* Address definitions for the TCO */
0070 /* TCO base address */
0071 #define TCOBASE(p)  ((p)->tco_res->start)
0072 /* SMI Control and Enable Register */
0073 #define SMI_EN(p)   ((p)->smi_res->start)
0074
0075 #define TCO_RLD(p)  (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */
0076 #define TCOv1_TMR(p)    (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
0077 #define TCO_DAT_IN(p)   (TCOBASE(p) + 0x02) /* TCO Data In Register */
0078 #define TCO_DAT_OUT(p)  (TCOBASE(p) + 0x03) /* TCO Data Out Register    */
0079 #define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
0080 #define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
0081 #define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register    */
0082 #define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register    */
0083 #define TCOv2_TMR(p)    (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
0084
0085 /* internal variables */
0086 struct iTCO_wdt_private {
0087     struct watchdog_device wddev;
0088
0089     /* TCO version/generation */
0090     unsigned int iTCO_version;
0091     struct resource *tco_res;
0092     struct resource *smi_res;
0093     /*
0094      * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
0095      * or memory-mapped PMC register bit 4 (TCO version 3).
0096      */
0097     unsigned long __iomem *gcs_pmc;
0098     /* the lock for io operations */
0099     spinlock_t io_lock;
0100     /* the PCI-device */
0101     struct pci_dev *pci_dev;
0102     /* whether or not the watchdog has been suspended */
0103     bool suspended;
0104     /* no reboot API private data */
0105     void *no_reboot_priv;
0106     /* no reboot update function pointer */
0107     int (*update_no_reboot_bit)(void *p, bool set);
0108 };
0109
0110 /* module parameters */
0111 #define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
0112 static int heartbeat = WATCHDOG_TIMEOUT;  /* in seconds */
0113 module_param(heartbeat, int, 0);
0114 MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
0115     "5..76 (TCO v1) or 3..614 (TCO v2), default="
0116                 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
0117
0118 static bool nowayout = WATCHDOG_NOWAYOUT;
0119 module_param(nowayout, bool, 0);
0120 MODULE_PARM_DESC(nowayout,
0121     "Watchdog cannot be stopped once started (default="
0122                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
0123
0124 static int turn_SMI_watchdog_clear_off = 1;
0125 module_param(turn_SMI_watchdog_clear_off, int, 0);
0126 MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
0127     "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
0128
0129 /*
0130  * Some TCO specific functions
0131  */
0132
0133 /*
0134  * The iTCO v1 and v2's internal timer is stored as ticks which decrement
0135  * every 0.6 seconds.  v3's internal timer is stored as seconds (some
0136  * datasheets incorrectly state 0.6 seconds).
0137  */
0138 static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p,
0139                         int secs)
0140 {
0141     return p->iTCO_version == 3 ? secs : (secs * 10) / 6;
0142 }
0143
0144 static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p,
0145                         int ticks)
0146 {
0147     return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10;
0148 }
0149
0150 static inline u32 no_reboot_bit(struct iTCO_wdt_private *p)
0151 {
0152     u32 enable_bit;
0153
0154     switch (p->iTCO_version) {
0155     case 5:
0156     case 3:
0157         enable_bit = 0x00000010;
0158         break;
0159     case 2:
0160         enable_bit = 0x00000020;
0161         break;
0162     case 4:
0163     case 1:
0164     default:
0165         enable_bit = 0x00000002;
0166         break;
0167     }
0168
0169     return enable_bit;
0170 }
0171
0172 static int update_no_reboot_bit_def(void *priv, bool set)
0173 {
0174     return 0;
0175 }
0176
0177 static int update_no_reboot_bit_pci(void *priv, bool set)
0178 {
0179     struct iTCO_wdt_private *p = priv;
0180     u32 val32 = 0, newval32 = 0;
0181
0182     pci_read_config_dword(p->pci_dev, 0xd4, &val32);
0183     if (set)
0184         val32 |= no_reboot_bit(p);
0185     else
0186         val32 &= ~no_reboot_bit(p);
0187     pci_write_config_dword(p->pci_dev, 0xd4, val32);
0188     pci_read_config_dword(p->pci_dev, 0xd4, &newval32);
0189
0190     /* make sure the update is successful */
0191     if (val32 != newval32)
0192         return -EIO;
0193
0194     return 0;
0195 }
0196
0197 static int update_no_reboot_bit_mem(void *priv, bool set)
0198 {
0199     struct iTCO_wdt_private *p = priv;
0200     u32 val32 = 0, newval32 = 0;
0201
0202     val32 = readl(p->gcs_pmc);
0203     if (set)
0204         val32 |= no_reboot_bit(p);
0205     else
0206         val32 &= ~no_reboot_bit(p);
0207     writel(val32, p->gcs_pmc);
0208     newval32 = readl(p->gcs_pmc);
0209
0210     /* make sure the update is successful */
0211     if (val32 != newval32)
0212         return -EIO;
0213
0214     return 0;
0215 }
0216
0217 static int update_no_reboot_bit_cnt(void *priv, bool set)
0218 {
0219     struct iTCO_wdt_private *p = priv;
0220     u16 val, newval;
0221
0222     val = inw(TCO1_CNT(p));
0223     if (set)
0224         val |= BIT(0);
0225     else
0226         val &= ~BIT(0);
0227     outw(val, TCO1_CNT(p));
0228     newval = inw(TCO1_CNT(p));
0229
0230     /* make sure the update is successful */
0231     return val != newval ? -EIO : 0;
0232 }
0233
0234 static int update_no_reboot_bit_pmc(void *priv, bool set)
0235 {
0236     struct intel_pmc_dev *pmc = priv;
0237     u32 bits = PMC_CFG_NO_REBOOT_EN;
0238     u32 value = set ? bits : 0;
0239
0240     return intel_pmc_gcr_update(pmc, PMC_GCR_PMC_CFG_REG, bits, value);
0241 }
0242
0243 static void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p,
0244                      struct platform_device *pdev,
0245                      struct itco_wdt_platform_data *pdata)
0246 {
0247     if (pdata->no_reboot_use_pmc) {
0248         struct intel_pmc_dev *pmc = dev_get_drvdata(pdev->dev.parent);
0249
0250         p->update_no_reboot_bit = update_no_reboot_bit_pmc;
0251         p->no_reboot_priv = pmc;
0252         return;
0253     }
0254
0255     if (p->iTCO_version >= 6)
0256         p->update_no_reboot_bit = update_no_reboot_bit_cnt;
0257     else if (p->iTCO_version >= 2)
0258         p->update_no_reboot_bit = update_no_reboot_bit_mem;
0259     else if (p->iTCO_version == 1)
0260         p->update_no_reboot_bit = update_no_reboot_bit_pci;
0261     else
0262         p->update_no_reboot_bit = update_no_reboot_bit_def;
0263
0264     p->no_reboot_priv = p;
0265 }
0266
0267 static int iTCO_wdt_start(struct watchdog_device *wd_dev)
0268 {
0269     struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
0270     unsigned int val;
0271
0272     spin_lock(&p->io_lock);
0273
0274     iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout);
0275
0276     /* disable chipset's NO_REBOOT bit */
0277     if (p->update_no_reboot_bit(p->no_reboot_priv, false)) {
0278         spin_unlock(&p->io_lock);
0279         dev_err(wd_dev->parent, "failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
0280         return -EIO;
0281     }
0282
0283     /* Force the timer to its reload value by writing to the TCO_RLD
0284        register */
0285     if (p->iTCO_version >= 2)
0286         outw(0x01, TCO_RLD(p));
0287     else if (p->iTCO_version == 1)
0288         outb(0x01, TCO_RLD(p));
0289
0290     /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
0291     val = inw(TCO1_CNT(p));
0292     val &= 0xf7ff;
0293     outw(val, TCO1_CNT(p));
0294     val = inw(TCO1_CNT(p));
0295     spin_unlock(&p->io_lock);
0296
0297     if (val & 0x0800)
0298         return -1;
0299     return 0;
0300 }
0301
0302 static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
0303 {
0304     struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
0305     unsigned int val;
0306
0307     spin_lock(&p->io_lock);
0308
0309     iTCO_vendor_pre_stop(p->smi_res);
0310
0311     /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
0312     val = inw(TCO1_CNT(p));
0313     val |= 0x0800;
0314     outw(val, TCO1_CNT(p));
0315     val = inw(TCO1_CNT(p));
0316
0317     /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
0318     p->update_no_reboot_bit(p->no_reboot_priv, true);
0319
0320     spin_unlock(&p->io_lock);
0321
0322     if ((val & 0x0800) == 0)
0323         return -1;
0324     return 0;
0325 }
0326
0327 static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
0328 {
0329     struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
0330
0331     spin_lock(&p->io_lock);
0332
0333     /* Reload the timer by writing to the TCO Timer Counter register */
0334     if (p->iTCO_version >= 2) {
0335         outw(0x01, TCO_RLD(p));
0336     } else if (p->iTCO_version == 1) {
0337         /* Reset the timeout status bit so that the timer
0338          * needs to count down twice again before rebooting */
0339         outw(0x0008, TCO1_STS(p));  /* write 1 to clear bit */
0340
0341         outb(0x01, TCO_RLD(p));
0342     }
0343
0344     spin_unlock(&p->io_lock);
0345     return 0;
0346 }
0347
0348 static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
0349 {
0350     struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
0351     unsigned int val16;
0352     unsigned char val8;
0353     unsigned int tmrval;
0354
0355     tmrval = seconds_to_ticks(p, t);
0356
0357     /* For TCO v1 the timer counts down twice before rebooting */
0358     if (p->iTCO_version == 1)
0359         tmrval /= 2;
0360
0361     /* from the specs: */
0362     /* "Values of 0h-3h are ignored and should not be attempted" */
0363     if (tmrval < 0x04)
0364         return -EINVAL;
0365     if ((p->iTCO_version >= 2 && tmrval > 0x3ff) ||
0366         (p->iTCO_version == 1 && tmrval > 0x03f))
0367         return -EINVAL;
0368
0369     /* Write new heartbeat to watchdog */
0370     if (p->iTCO_version >= 2) {
0371         spin_lock(&p->io_lock);
0372         val16 = inw(TCOv2_TMR(p));
0373         val16 &= 0xfc00;
0374         val16 |= tmrval;
0375         outw(val16, TCOv2_TMR(p));
0376         val16 = inw(TCOv2_TMR(p));
0377         spin_unlock(&p->io_lock);
0378
0379         if ((val16 & 0x3ff) != tmrval)
0380             return -EINVAL;
0381     } else if (p->iTCO_version == 1) {
0382         spin_lock(&p->io_lock);
0383         val8 = inb(TCOv1_TMR(p));
0384         val8 &= 0xc0;
0385         val8 |= (tmrval & 0xff);
0386         outb(val8, TCOv1_TMR(p));
0387         val8 = inb(TCOv1_TMR(p));
0388         spin_unlock(&p->io_lock);
0389
0390         if ((val8 & 0x3f) != tmrval)
0391             return -EINVAL;
0392     }
0393
0394     wd_dev->timeout = t;
0395     return 0;
0396 }
0397
0398 static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
0399 {
0400     struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
0401     unsigned int val16;
0402     unsigned char val8;
0403     unsigned int time_left = 0;
0404
0405     /* read the TCO Timer */
0406     if (p->iTCO_version >= 2) {
0407         spin_lock(&p->io_lock);
0408         val16 = inw(TCO_RLD(p));
0409         val16 &= 0x3ff;
0410         spin_unlock(&p->io_lock);
0411
0412         time_left = ticks_to_seconds(p, val16);
0413     } else if (p->iTCO_version == 1) {
0414         spin_lock(&p->io_lock);
0415         val8 = inb(TCO_RLD(p));
0416         val8 &= 0x3f;
0417         if (!(inw(TCO1_STS(p)) & 0x0008))
0418             val8 += (inb(TCOv1_TMR(p)) & 0x3f);
0419         spin_unlock(&p->io_lock);
0420
0421         time_left = ticks_to_seconds(p, val8);
0422     }
0423     return time_left;
0424 }
0425
0426 static void iTCO_wdt_set_running(struct iTCO_wdt_private *p)
0427 {
0428     u16 val;
0429
0430     /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is * enabled */
0431     val = inw(TCO1_CNT(p));
0432     if (!(val & BIT(11)))
0433         set_bit(WDOG_HW_RUNNING, &p->wddev.status);
0434 }
0435
0436 /*
0437  *  Kernel Interfaces
0438  */
0439
0440 static const struct watchdog_info ident = {
0441     .options =      WDIOF_SETTIMEOUT |
0442                 WDIOF_KEEPALIVEPING |
0443                 WDIOF_MAGICCLOSE,
0444     .firmware_version = 0,
0445     .identity =     DRV_NAME,
0446 };
0447
0448 static const struct watchdog_ops iTCO_wdt_ops = {
0449     .owner =        THIS_MODULE,
0450     .start =        iTCO_wdt_start,
0451     .stop =         iTCO_wdt_stop,
0452     .ping =         iTCO_wdt_ping,
0453     .set_timeout =      iTCO_wdt_set_timeout,
0454     .get_timeleft =     iTCO_wdt_get_timeleft,
0455 };
0456
0457 /*
0458  *  Init & exit routines
0459  */
0460
0461 static int iTCO_wdt_probe(struct platform_device *pdev)
0462 {
0463     struct device *dev = &pdev->dev;
0464     struct itco_wdt_platform_data *pdata = dev_get_platdata(dev);
0465     struct iTCO_wdt_private *p;
0466     unsigned long val32;
0467     int ret;
0468
0469     if (!pdata)
0470         return -ENODEV;
0471
0472     p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
0473     if (!p)
0474         return -ENOMEM;
0475
0476     spin_lock_init(&p->io_lock);
0477
0478     p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO);
0479     if (!p->tco_res)
0480         return -ENODEV;
0481
0482     p->iTCO_version = pdata->version;
0483     p->pci_dev = to_pci_dev(dev->parent);
0484
0485     p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI);
0486     if (p->smi_res) {
0487         /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
0488         if (!devm_request_region(dev, p->smi_res->start,
0489                      resource_size(p->smi_res),
0490                      pdev->name)) {
0491             dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n",
0492                    (u64)SMI_EN(p));
0493             return -EBUSY;
0494         }
0495     } else if (iTCO_vendorsupport ||
0496            turn_SMI_watchdog_clear_off >= p->iTCO_version) {
0497         dev_err(dev, "SMI I/O resource is missing\n");
0498         return -ENODEV;
0499     }
0500
0501     iTCO_wdt_no_reboot_bit_setup(p, pdev, pdata);
0502
0503     /*
0504      * Get the Memory-Mapped GCS or PMC register, we need it for the
0505      * NO_REBOOT flag (TCO v2 and v3).
0506      */
0507     if (p->iTCO_version >= 2 && p->iTCO_version < 6 &&
0508         !pdata->no_reboot_use_pmc) {
0509         p->gcs_pmc = devm_platform_ioremap_resource(pdev, ICH_RES_MEM_GCS_PMC);
0510         if (IS_ERR(p->gcs_pmc))
0511             return PTR_ERR(p->gcs_pmc);
0512     }
0513
0514     /* Check chipset's NO_REBOOT bit */
0515     if (p->update_no_reboot_bit(p->no_reboot_priv, false) &&
0516         iTCO_vendor_check_noreboot_on()) {
0517         dev_info(dev, "unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
0518         return -ENODEV; /* Cannot reset NO_REBOOT bit */
0519     }
0520
0521     /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
0522     p->update_no_reboot_bit(p->no_reboot_priv, true);
0523
0524     if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
0525         /*
0526          * Bit 13: TCO_EN -> 0
0527          * Disables TCO logic generating an SMI#
0528          */
0529         val32 = inl(SMI_EN(p));
0530         val32 &= 0xffffdfff;    /* Turn off SMI clearing watchdog */
0531         outl(val32, SMI_EN(p));
0532     }
0533
0534     if (!devm_request_region(dev, p->tco_res->start,
0535                  resource_size(p->tco_res),
0536                  pdev->name)) {
0537         dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n",
0538                (u64)TCOBASE(p));
0539         return -EBUSY;
0540     }
0541
0542     dev_info(dev, "Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
0543         pdata->name, pdata->version, (u64)TCOBASE(p));
0544
0545     /* Clear out the (probably old) status */
0546     switch (p->iTCO_version) {
0547     case 6:
0548     case 5:
0549     case 4:
0550         outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
0551         outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
0552         break;
0553     case 3:
0554         outl(0x20008, TCO1_STS(p));
0555         break;
0556     case 2:
0557     case 1:
0558     default:
0559         outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
0560         outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
0561         outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */
0562         break;
0563     }
0564
0565     p->wddev.info = &ident,
0566     p->wddev.ops = &iTCO_wdt_ops,
0567     p->wddev.bootstatus = 0;
0568     p->wddev.timeout = WATCHDOG_TIMEOUT;
0569     watchdog_set_nowayout(&p->wddev, nowayout);
0570     p->wddev.parent = dev;
0571
0572     watchdog_set_drvdata(&p->wddev, p);
0573     platform_set_drvdata(pdev, p);
0574
0575     iTCO_wdt_set_running(p);
0576
0577     /* Check that the heartbeat value is within it's range;
0578        if not reset to the default */
0579     if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) {
0580         iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT);
0581         dev_info(dev, "timeout value out of range, using %d\n",
0582             WATCHDOG_TIMEOUT);
0583     }
0584
0585     watchdog_stop_on_reboot(&p->wddev);
0586     watchdog_stop_on_unregister(&p->wddev);
0587     ret = devm_watchdog_register_device(dev, &p->wddev);
0588     if (ret != 0) {
0589         dev_err(dev, "cannot register watchdog device (err=%d)\n", ret);
0590         return ret;
0591     }
0592
0593     dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
0594         heartbeat, nowayout);
0595
0596     return 0;
0597 }
0598
0599 /*
0600  * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so
0601  * the watchdog cannot be pinged while in that state.  In ACPI sleep states the
0602  * watchdog is stopped by the platform firmware.
0603  */
0604
0605 #ifdef CONFIG_ACPI
0606 static inline bool __maybe_unused need_suspend(void)
0607 {
0608     return acpi_target_system_state() == ACPI_STATE_S0;
0609 }
0610 #else
0611 static inline bool __maybe_unused need_suspend(void) { return true; }
0612 #endif
0613
0614 static int __maybe_unused iTCO_wdt_suspend_noirq(struct device *dev)
0615 {
0616     struct iTCO_wdt_private *p = dev_get_drvdata(dev);
0617     int ret = 0;
0618
0619     p->suspended = false;
0620     if (watchdog_active(&p->wddev) && need_suspend()) {
0621         ret = iTCO_wdt_stop(&p->wddev);
0622         if (!ret)
0623             p->suspended = true;
0624     }
0625     return ret;
0626 }
0627
0628 static int __maybe_unused iTCO_wdt_resume_noirq(struct device *dev)
0629 {
0630     struct iTCO_wdt_private *p = dev_get_drvdata(dev);
0631
0632     if (p->suspended)
0633         iTCO_wdt_start(&p->wddev);
0634
0635     return 0;
0636 }
0637
0638 static const struct dev_pm_ops iTCO_wdt_pm = {
0639     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(iTCO_wdt_suspend_noirq,
0640                       iTCO_wdt_resume_noirq)
0641 };
0642
0643 static struct platform_driver iTCO_wdt_driver = {
0644     .probe          = iTCO_wdt_probe,
0645     .driver         = {
0646         .name   = DRV_NAME,
0647         .pm     = &iTCO_wdt_pm,
0648     },
0649 };
0650
0651 module_platform_driver(iTCO_wdt_driver);
0652
0653 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
0654 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
0655 MODULE_VERSION(DRV_VERSION);
0656 MODULE_LICENSE("GPL");
0657 MODULE_ALIAS("platform:" DRV_NAME);